Lines Matching refs:BuildMI
174 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
186 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
189 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
711 BuildMI(MBB, MBBI, DL,
755 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
762 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
777 BuildMI(MBB, MBBI, DL,
785 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
816 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label);
837 BuildMI(MBB, MBBI, DL,
891 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
899 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
905 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
910 BuildMI(MBB, MBBI, DL,
920 BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64rr), StackPtr)
928 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
945 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
953 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
1038 BuildMI(MBB, MBBI, DL,
1072 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
1076 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
1090 BuildMI(MBB, MBBI, DL,
1124 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
1136 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
1141 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)).
1144 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
1255 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1313 BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
1482 BuildMI(checkMBB, DL, TII.get(X86::LEA64r), ScratchReg).addReg(X86::RSP)
1485 BuildMI(checkMBB, DL, TII.get(X86::CMP64rm)).addReg(ScratchReg)
1506 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1510 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1534 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
1537 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
1539 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
1546 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
1552 BuildMI(checkMBB, DL, TII.get(X86::JA_4)).addMBB(&prologueMBB);
1561 BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10);
1563 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R10)
1565 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R11)
1570 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1572 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1578 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1581 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1585 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
1587 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
1717 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
1720 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
1722 BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_4)).addMBB(&prologueMBB);
1725 BuildMI(incStackMBB, DL, TII.get(CALLop)).
1727 addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
1729 addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
1731 BuildMI(incStackMBB, DL, TII.get(X86::JLE_4)).addMBB(incStackMBB);
1774 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(IsLP64, Amount)),
1786 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
1807 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
