Lines Matching defs:N1
7630 SDValue N1 = Op.getOperand(1);
7648 if (N1.getValueType() != MVT::i32)
7649 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7652 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7666 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7667 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7684 SDValue N1 = Op.getOperand(1);
7701 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7717 if (N1.getValueType() != MVT::i32)
7718 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7721 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
16702 SDValue N1 = N->getOperand(1);
16703 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
16729 if (isSplatVector(N1.getNode())) {
16731 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
16805 SDValue N1 = N->getOperand(1);
16807 SDValue CMP1 = N1->getOperand(1);
16839 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
16926 SDValue N1 = Narrow->getOperand(1);
16939 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
16940 bool RHSConst = (isSplatVector(N1.getNode()) &&
16941 isa<ConstantSDNode>(N1->getOperand(0)));
16950 // Set N0 and N1 to hold the inputs to the new wide operation.
16953 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
16954 N1->getOperand(0));
16955 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
16956 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
16958 N1 = N1->getOperand(0);
16962 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
16998 SDValue N1 = N->getOperand(1);
17002 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
17004 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
17007 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
17008 isZero(N1.getOperand(0)))
17012 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
17014 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
17017 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
17018 isAllOnes(N1.getOperand(1)))
17032 SDValue N1 = N->getOperand(1);
17039 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
17042 if (N1.getOpcode() == ISD::XOR &&
17043 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
17044 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
17045 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
17062 SDValue N1 = N->getOperand(1);
17072 std::swap(N0, N1);
17074 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
17075 SDValue Mask = N1.getOperand(0);
17076 SDValue X = N1.getOperand(1);
17148 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
17149 std::swap(N0, N1);
17150 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
17152 if (!N0.hasOneUse() || !N1.hasOneUse())
17158 SDValue ShAmt1 = N1.getOperand(1);
17169 SDValue Op1 = N1.getOperand(0);
17194 N0.getOperand(0), N1.getOperand(0),
17212 SDValue N1 = N->getOperand(1);
17219 N0.getOperand(1) == N1 &&
17220 N1.getOpcode() == ISD::SRA &&
17221 N1.getOperand(0) == N0.getOperand(0))
17222 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
17262 SDValue N1 = N->getOperand(1);
17265 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
17267 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
17269 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
17270 isAllOnes(N1.getOperand(1)))
17963 SDValue N1 = N->getOperand(1);
17964 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
17984 N00, N1);
18491 SDValue N1 = Op.getOperand(1);
18492 if (!Commute && MayFoldLoad(N1))
18495 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
18497 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
