Lines Matching full:setcc
226 // X86 is weird, it always uses i8 for shift amounts and setcc results.
517 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
518 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
519 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
520 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
521 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
522 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
525 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
846 setOperationAction(ISD::SETCC, VT, Expand);
956 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
957 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
958 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
959 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
1180 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1181 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1182 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1183 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1362 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1363 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1520 setTargetDAGCombine(ISD::SETCC);
5656 if (In.getOpcode() == ISD::SETCC) {
5668 } else if (In.getOpcode() == X86ISD::SETCC) {
9296 // Truncate operations may prevent the merge of the SETCC instruction
9330 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
9336 UI->getOpcode() != ISD::SETCC &&
9376 User->getOpcode() != ISD::SETCC &&
9438 // from the setcc node.
9586 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9610 default: llvm_unreachable("Unexpected SETCC condition");
9643 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9720 default: llvm_unreachable("Unexpected SETCC condition");
9848 assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
9874 // If the input is a setcc, then reuse the input setcc or use a new one with
9876 if (Op0.getOpcode() == X86ISD::SETCC) {
9883 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9895 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9952 if (Cond.getOpcode() == ISD::SETCC &&
9970 if (Cond.getOpcode() == ISD::SETCC) {
9980 if (Cond.getOpcode() == X86ISD::SETCC &&
10035 // setting operand in place of the X86ISD::SETCC.
10037 if (CondOpcode == X86ISD::SETCC ||
10200 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
10206 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10208 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
10212 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
10213 // 1 and that the SETCC node has a single use.
10219 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10234 if (Cond.getOpcode() == ISD::SETCC) {
10235 // Check for setcc([su]{add,sub,mul}o == 0).
10272 // setting operand in place of the X86ISD::SETCC.
10274 if (CondOpcode == X86ISD::SETCC ||
10387 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
10396 } else if (Cond.getOpcode() == ISD::SETCC &&
10427 } else if (Cond.getOpcode() == ISD::SETCC &&
10847 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10849 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11084 // or testp pattern and a setcc for the result.
11144 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11145 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11300 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11303 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11429 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11432 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
12431 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
12432 // looks for this combo and may remove the "setcc" instruction if the "setcc"
12483 SDValue SetCC =
12484 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12488 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
12496 SDValue SetCC =
12497 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
12501 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
12835 case ISD::SETCC: return LowerSETCC(Op, DAG);
13131 case X86ISD::SETCC: return "X86ISD::SETCC";
15429 case X86ISD::SETCC:
15934 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
16086 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
16108 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
16182 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
16200 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
16255 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC)
16261 Cond.getOpcode() == ISD::SETCC) {
16332 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
16336 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
16337 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
16340 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
16341 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
16357 // an SetCC or extended from it.
16361 SDValue SetCC;
16367 SetCC = Op2;
16369 SetCC = Op1;
16382 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
16383 SetCC.getOpcode() == ISD::TRUNCATE ||
16384 SetCC.getOpcode() == ISD::AND) {
16385 if (SetCC.getOpcode() == ISD::AND) {
16388 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
16391 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
16396 SetCC = SetCC.getOperand(OpIdx);
16399 SetCC = SetCC.getOperand(0);
16402 switch (SetCC.getOpcode()) {
16410 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
16413 case X86ISD::SETCC:
16415 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
16418 return SetCC.getOperand(1);
16421 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
16422 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
16428 SDValue Op = SetCC.getOperand(0);
16453 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
16456 return SetCC.getOperand(3);
16514 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
16518 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16532 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
16535 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16573 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16793 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
18056 // ISD::SETCC is always legalized to i8.
18121 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
18158 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
18255 SDValue SetCC = Ext.getOperand(0);
18256 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
18259 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
18263 SDValue Cmp = SetCC.getOperand(1);
18386 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
18387 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
