Lines Matching full:vectors
160 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
878 // MMX-sized vectors (other than x86mmx) are expected to be expanded
970 // Do not attempt to custom lower non-power-of-2 vectors
973 // Do not attempt to custom lower non-128-bit vectors
997 // Do not attempt to promote non-128-bit vectors
1069 // i8 and i16 vectors are custom , because the source register and source
1070 // source memory operand types are not the same width. f32 vectors are
1266 // Do not attempt to custom lower other non-256-bit vectors
1283 // Do not attempt to promote non-256-bit vectors
1408 // Do not attempt to custom lower other non-512-bit vectors
1433 // Do not attempt to promote non-256-bit vectors
1575 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1809 // or SSE or MMX vectors.
4240 /// suitable for instruction that extract 128 or 256 bit vectors
4554 // Vectors of all-zeros and all-ones are materialized with special
4637 // Always build SSE zero vectors as <4 x i32> bitcasted
4656 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4669 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4819 // to use VPERM* to shuffle the vectors
5061 // check if they consecutively come from only one of the source vectors.
5095 // check if they consecutively come from only one of the source vectors.
5120 // shift instructions which handle more than 128-bit vectors.
5579 // Quit if more than 2 vectors to shuffle
5715 // Generate vectors for predicate vectors.
5719 // Vectors containing all zeros can be matched by pxor and xorps later
5721 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5729 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5730 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5731 // vpcmpeqd on 256-bit vectors.
5766 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5894 // For AVX-length vectors, build the individual 128-bit pieces and use
6029 // rounds because they will permute elements within both vectors.
6044 // to create 256-bit vectors from two other 128-bit ones.
6064 // AVX/AVX-512 can use the vinsertf128 instruction to create 256-bit vectors
6110 // Convert i32 vectors to floating point if it is not AVX2.
6111 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
6179 // of the two input vectors, shuffle them into one input vector so only a
6267 // If we have elements from both input vectors, set the high bit of the
6410 // Otherwise, we have elements from both input vectors, and must zero out
6445 // the 16 different words that comprise the two doublequadword input vectors.
6635 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6657 // input vectors to use as shuffle operands (recorded in InputUsed).
6692 // More than two input vectors used! Give up on trying to create a
6728 // No input vectors were used! The result is undefined.
6749 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
7182 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
7194 // Normalize the input vectors. Here splats, zeroed vectors, profitable
7457 // Handle all 128-bit wide vectors with 4 elements, and match them with
8758 // Optimize vectors in AVX mode:
9245 // Cast all vectors into TestVT for PTEST.
9249 // If more than one full vectors are evaluated, OR them first before PTEST.
9252 // 1 node left, i.e. the final OR'd value of all vectors.
9650 // Extract the LHS vectors
9655 // Extract the RHS vectors
10166 // Optimize vectors in AVX mode
10173 // concat the vectors to original VT
11848 // Extract the LHS vectors
11853 // Extract the RHS vectors
11910 // Merge the two vectors back together with a shuffle. This expands into 2
11935 // Bit cast to 32-bit vectors for MULUDQ
12393 // Extract the two vectors
12397 // Recreate the shift amount vectors
12527 // Extract the LHS vectors
13425 // Very little shuffling can be done for 64-bit vectors right now.
15521 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
15771 // Only operate on vectors of 4 elements, where the alternative shuffling
16201 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
16875 // Match direct AllOnes for 128 and 256-bit vectors
17789 // Check that the shuffles are both shuffling the same vectors.
