Lines Matching refs:MVT
224 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
286 addRegisterClass(MVT::i8, &X86::GR8RegClass);
287 addRegisterClass(MVT::i16, &X86::GR16RegClass);
288 addRegisterClass(MVT::i32, &X86::GR32RegClass);
290 addRegisterClass(MVT::i64, &X86::GR64RegClass);
292 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
295 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
296 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
297 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
298 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
299 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
300 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
303 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
304 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
305 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
306 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
307 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
308 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
312 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
313 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
314 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
317 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
318 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
322 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
325 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
330 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
331 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
336 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
338 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
340 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
341 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
344 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
345 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
350 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
351 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
355 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
356 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
359 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
361 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
363 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
364 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
369 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
370 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
371 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
374 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
375 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
382 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
386 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
397 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
398 MVT::i32 , Expand);
400 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
402 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
417 MVT VT = IntVTs[i];
425 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
432 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
433 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
434 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
435 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
436 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
437 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
438 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
439 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
440 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
441 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
443 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
444 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
445 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
446 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
447 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
448 setOperationAction(ISD::FREM , MVT::f32 , Expand);
449 setOperationAction(ISD::FREM , MVT::f64 , Expand);
450 setOperationAction(ISD::FREM , MVT::f80 , Expand);
451 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
455 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
456 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
457 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
458 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
460 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
461 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
463 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
465 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
466 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
468 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
474 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
475 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
476 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
477 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
478 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
479 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
481 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
483 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
484 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
485 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
486 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
487 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
488 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
490 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
491 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
496 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
498 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
499 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
500 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
502 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
505 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
506 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
509 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
511 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
512 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
513 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
514 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
515 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
516 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
517 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
518 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
519 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
520 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
521 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
522 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
524 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
525 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
527 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
534 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
535 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
538 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
539 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
540 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
541 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
543 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
544 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
545 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
547 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
548 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
549 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
550 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
551 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
554 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
555 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
556 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
558 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
559 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
560 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
564 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
566 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
570 MVT VT = IntVTs[i];
577 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
578 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
579 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
580 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
581 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
582 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
583 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
584 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
585 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
586 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
587 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
588 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
592 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
599 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
609 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
610 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
612 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
613 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
615 setOperationAction(ISD::TRAP, MVT::Other, Legal);
616 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
619 setOperationAction(ISD::VASTART , MVT::Other, Custom);
620 setOperationAction(ISD::VAEND , MVT::Other, Expand);
623 setOperationAction(ISD::VAARG , MVT::Other, Custom);
624 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
627 setOperationAction(ISD::VAARG , MVT::Other, Expand);
628 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
631 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
632 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
636 MVT::i64 : MVT::i32, Custom);
639 MVT::i64 : MVT::i32, Custom);
642 MVT::i64 : MVT::i32, Expand);
647 addRegisterClass(MVT::f32, &X86::FR32RegClass);
648 addRegisterClass(MVT::f64, &X86::FR64RegClass);
651 setOperationAction(ISD::FABS , MVT::f64, Custom);
652 setOperationAction(ISD::FABS , MVT::f32, Custom);
655 setOperationAction(ISD::FNEG , MVT::f64, Custom);
656 setOperationAction(ISD::FNEG , MVT::f32, Custom);
659 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
660 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
663 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
664 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
667 setOperationAction(ISD::FSIN , MVT::f64, Expand);
668 setOperationAction(ISD::FCOS , MVT::f64, Expand);
669 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
670 setOperationAction(ISD::FSIN , MVT::f32, Expand);
671 setOperationAction(ISD::FCOS , MVT::f32, Expand);
672 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
681 addRegisterClass(MVT::f32, &X86::FR32RegClass);
682 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
685 setOperationAction(ISD::FABS , MVT::f32, Custom);
688 setOperationAction(ISD::FNEG , MVT::f32, Custom);
690 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
693 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
694 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
697 setOperationAction(ISD::FSIN , MVT::f32, Expand);
698 setOperationAction(ISD::FCOS , MVT::f32, Expand);
699 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
709 setOperationAction(ISD::FSIN , MVT::f64, Expand);
710 setOperationAction(ISD::FCOS , MVT::f64, Expand);
711 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
716 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
717 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
719 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
720 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
721 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
722 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
725 setOperationAction(ISD::FSIN , MVT::f64, Expand);
726 setOperationAction(ISD::FSIN , MVT::f32, Expand);
727 setOperationAction(ISD::FCOS , MVT::f64, Expand);
728 setOperationAction(ISD::FCOS , MVT::f32, Expand);
729 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
730 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
743 setOperationAction(ISD::FMA, MVT::f64, Expand);
744 setOperationAction(ISD::FMA, MVT::f32, Expand);
748 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
749 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
750 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
767 setOperationAction(ISD::FSIN , MVT::f80, Expand);
768 setOperationAction(ISD::FCOS , MVT::f80, Expand);
769 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
772 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
773 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
774 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
775 setOperationAction(ISD::FRINT, MVT::f80, Expand);
776 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
777 setOperationAction(ISD::FMA, MVT::f80, Expand);
781 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
782 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
783 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
785 setOperationAction(ISD::FLOG, MVT::f80, Expand);
786 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
787 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
788 setOperationAction(ISD::FEXP, MVT::f80, Expand);
789 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
794 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
795 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
796 MVT VT = (MVT::SimpleValueType)i;
862 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
863 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
865 (MVT::SimpleValueType)InnerVT, Expand);
874 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
880 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
881 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
882 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
883 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
884 setOperationAction(ISD::AND, MVT::v8i8, Expand);
885 setOperationAction(ISD::AND, MVT::v4i16, Expand);
886 setOperationAction(ISD::AND, MVT::v2i32, Expand);
887 setOperationAction(ISD::AND, MVT::v1i64, Expand);
888 setOperationAction(ISD::OR, MVT::v8i8, Expand);
889 setOperationAction(ISD::OR, MVT::v4i16, Expand);
890 setOperationAction(ISD::OR, MVT::v2i32, Expand);
891 setOperationAction(ISD::OR, MVT::v1i64, Expand);
892 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
893 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
894 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
895 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
896 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
897 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
898 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
899 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
900 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
901 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
902 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
903 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
904 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
905 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
906 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
907 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
908 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
911 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
913 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
914 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
915 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
916 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
917 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
918 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
919 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
920 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
921 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
922 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
923 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
924 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
928 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
932 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
933 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
934 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
935 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
937 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
938 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
939 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
940 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
941 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
942 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
943 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
944 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
945 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
946 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
947 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
948 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
949 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
950 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
951 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
952 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
953 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
954 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
956 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
957 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
958 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
959 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
961 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
962 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
963 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
968 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
969 MVT VT = (MVT::SimpleValueType)i;
981 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
982 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
983 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
984 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
985 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
986 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
989 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
990 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
994 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
995 MVT VT = (MVT::SimpleValueType)i;
1002 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1004 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1006 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1008 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1010 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1013 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1016 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1017 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1018 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1019 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1021 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1022 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1024 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1025 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1029 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1031 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1032 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1034 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1038 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1039 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1040 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1041 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1042 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1043 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1044 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1045 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1046 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1047 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1049 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1050 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1051 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1052 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1053 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1054 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1055 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1056 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1057 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1058 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1061 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1063 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
1064 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1073 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1074 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT
1075 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1076 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1078 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1079 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1080 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1081 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1086 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1087 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1092 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1093 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1095 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1096 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1098 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1099 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1103 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1104 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1106 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1107 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1109 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1111 setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1112 setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1116 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1117 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1118 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1119 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1120 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1121 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1123 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1124 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1125 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1127 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1128 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1129 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1130 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1131 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1132 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1133 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1134 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1135 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1136 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1137 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1138 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1140 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1141 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1142 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1143 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1144 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1145 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1146 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1147 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1148 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1149 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1150 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1151 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1153 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1154 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1156 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1158 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1159 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1160 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1161 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1163 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1164 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1165 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1167 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1169 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1170 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1172 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1173 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1175 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1176 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1178 setOperationAction(ISD::SDIV, MVT::v16i16, Custom);
1180 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1181 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1182 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1183 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1185 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1186 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1187 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1189 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1190 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1191 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1192 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1195 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1196 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1197 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1198 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1199 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1202 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1203 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1205 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1206 setOperationAction(ISD::FMA, MVT::f32, Legal);
1207 setOperationAction(ISD::FMA, MVT::f64, Legal);
1211 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1212 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1213 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1214 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1216 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1217 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1218 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1219 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1221 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1222 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1223 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1226 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1228 setOperationAction(ISD::SDIV, MVT::v8i32, Custom);
1230 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1231 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1232 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1233 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1236 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1237 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1238 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1240 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1241 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1242 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1248 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1249 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1254 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1257 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1258 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1259 MVT VT = (MVT::SimpleValueType)i;
1280 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1281 MVT VT = (MVT::SimpleValueType)i;
1288 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1290 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1292 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1294 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1296 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1301 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1302 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1303 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1304 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1307 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1309 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1310 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1311 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1312 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1313 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1314 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1316 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1317 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1318 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1319 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1320 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1321 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1323 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1324 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1325 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1326 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1327 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1328 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1329 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1330 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1331 setOperationAction(ISD::SDIV, MVT::v16i32, Custom);
1334 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1335 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1336 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1337 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1338 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1339 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1340 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1341 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1343 setOperationAction(ISD::TRUNCATE, MVT::i1, Legal);
1344 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1345 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1346 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1347 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1348 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1349 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1350 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1351 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1352 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1353 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1354 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1356 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1357 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1358 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1359 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1360 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1362 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1363 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1365 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1367 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1368 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1369 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1370 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1371 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1373 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1374 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1376 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1377 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1379 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1381 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1382 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1384 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1385 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1387 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1388 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1390 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1391 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1392 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1395 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1396 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1397 MVT VT = (MVT::SimpleValueType)i;
1405 if (VT.getVectorElementType() == MVT::i1)
1412 if (VT != MVT::v8i64) {
1414 AddPromotedToType (ISD::XOR, VT, MVT::v8i64);
1416 AddPromotedToType (ISD::OR, VT, MVT::v8i64);
1418 AddPromotedToType (ISD::AND, VT, MVT::v8i64);
1430 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1431 MVT VT = (MVT::SimpleValueType)i;
1438 AddPromotedToType (ISD::LOAD, VT, MVT::v8i64);
1440 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1446 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1447 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1448 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1453 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1454 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1464 MVT VT = IntVTs[i];
1474 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1475 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1492 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1493 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1544 if (!VT.isVector()) return MVT::i8;
1619 return MVT::v8i32;
1621 return MVT::v8f32;
1624 return MVT::v4i32;
1626 return MVT::v4f32;
1632 return MVT::f64;
1636 return MVT::i64;
1637 return MVT::i32;
1640 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1641 if (VT == MVT::f32)
1643 else if (VT == MVT::f64)
1708 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1714 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1719 case MVT::x86mmx:
1722 case MVT::f32: case MVT::f64:
1723 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1724 case MVT::v4f32: case MVT::v2f64:
1725 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1726 case MVT::v4f64:
1789 MVT::i16));
1810 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1818 MVT::f64 &&
1829 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1838 if (ValVT == MVT::x86mmx) {
1840 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1841 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1846 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1887 MVT::Other, &RetOps[0], RetOps.size());
1901 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1922 MVT
1923 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1925 MVT ReturnMVT;
1927 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1928 ReturnMVT = MVT::i8;
1930 ReturnMVT = MVT::i32;
1932 MVT MinVT = getRegisterType(ReturnMVT);
1959 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1974 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1977 MVT::Other, MVT::Glue, Ops), 1);
2051 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2182 if (RegVT == MVT::i32)
2184 else if (Is64Bit && RegVT == MVT::i64)
2186 else if (RegVT == MVT::f32)
2188 else if (RegVT == MVT::f64)
2196 else if (RegVT == MVT::x86mmx)
2198 else if (RegVT == MVT::v8i1)
2200 else if (RegVT == MVT::v16i1)
2250 MVT PtrTy = getPointerTy();
2255 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2348 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2364 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2375 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2379 MVT::Other,
2384 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2584 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2585 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2586 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2631 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2678 DAG.getConstant(NumXMMRegs, MVT::i8)));
2731 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2831 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2844 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3283 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3296 DAG.getConstant(TargetMask, MVT::i8));
3536 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3538 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3546 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3558 if (VT == MVT::v16i16) {
3575 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3587 if (VT == MVT::v16i16) {
3830 MVT VT = SVOp->getValueType(0).getSimpleVT();
3833 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4075 MVT VT = SVOp->getValueType(0).getSimpleVT();
4250 MVT VT = N->getValueType(0).getSimpleVT();
4268 MVT VT = N->getValueType(0).getSimpleVT();
4295 MVT VT = N->getValueType(0).getSimpleVT();
4325 MVT VT = N->getValueType(0).getSimpleVT();
4327 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4349 MVT VT = N->getValueType(0).getSimpleVT();
4351 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4373 MVT VT = SVOp->getValueType(0).getSimpleVT();
4402 MVT VecVT = N->getOperand(0).getValueType().getSimpleVT();
4403 MVT ElVT = VecVT.getVectorElementType();
4417 MVT VecVT = N->getValueType(0).getSimpleVT();
4418 MVT ElVT = VecVT.getVectorElementType();
4456 MVT VT = N->getValueType(0).getSimpleVT();
4487 MVT VT = SVOp->getValueType(0).getSimpleVT();
4642 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4643 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4645 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4646 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4650 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4652 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4657 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4659 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops,
4672 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4676 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4681 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4684 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4685 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4688 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4768 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4770 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4779 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4780 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4814 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4849 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4953 MVT ShufVT = V.getValueType().getSimpleVT();
5148 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5150 V = DAG.getUNDEF(MVT::v8i16);
5159 MVT::i16, Op.getOperand(i-1));
5162 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5163 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5164 ThisElt, DAG.getConstant(8, MVT::i8));
5166 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5171 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5176 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5197 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5199 V = DAG.getUNDEF(MVT::v8i16);
5203 MVT::v8i16, V, Op.getOperand(i),
5217 EVT ShVT = MVT::v2i64;
5238 if (PVT != MVT::i32 && PVT != MVT::f32)
5356 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5367 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5368 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5372 array_lengthof(Ops), MVT::i64,
5382 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5406 MVT VT = Op.getValueType().getSimpleVT();
5610 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5615 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5623 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5645 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5646 DAG.getConstant(Immediate, MVT::i16));
5665 X86CC = DAG.getConstant(X86CCVal, MVT::i8);
5682 MVT InVT = In.getValueType().getSimpleVT();
5685 X86CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5688 if (VT == MVT::v16i1) {
5689 SDValue Cst1 = DAG.getConstant(-1, MVT::i16);
5690 SDValue Cst0 = DAG.getConstant(0, MVT::i16);
5691 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i16,
5696 if (VT == MVT::v8i1) {
5697 SDValue Cst1 = DAG.getConstant(-1, MVT::i32);
5698 SDValue Cst0 = DAG.getConstant(0, MVT::i32);
5699 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i32,
5701 CmovOp = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CmovOp);
5711 MVT VT = Op.getValueType().getSimpleVT();
5712 MVT ExtVT = VT.getVectorElementType();
5716 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5723 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5733 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5780 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5784 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5785 EVT VecVT = MVT::v4i32;
5790 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5816 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5817 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5829 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5830 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5831 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5833 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6047 MVT ResVT = Op.getValueType().getSimpleVT();
6076 MVT VT = SVOp->getValueType(0).getSimpleVT();
6077 MVT EltVT = VT.getVectorElementType();
6080 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
6082 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
6112 MVT BlendVT = VT;
6113 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
6114 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
6121 DAG.getConstant(MaskValue, MVT::i32));
6204 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
6205 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
6206 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
6207 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
6246 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
6247 MVT::v8i16), &MaskVals[0]);
6252 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
6276 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6277 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6279 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
6280 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6282 MVT::v16i8, &pshufbMask[0], 16));
6284 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6293 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6294 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6296 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
6297 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6299 MVT::v16i8, &pshufbMask[0], 16));
6300 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6301 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6318 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6323 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
6342 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6347 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
6371 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
6373 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
6375 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
6417 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6419 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6421 MVT::v16i8, &pshufbMask[0], 16));
6435 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6437 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6439 MVT::v16i8, &pshufbMask[0], 16));
6440 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6446 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6447 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6468 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6470 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6479 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6482 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6486 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6487 DAG.getConstant(0xFF00, MVT::i16));
6494 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6497 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6501 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6502 DAG.getConstant(0x00FF, MVT::i16));
6503 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6506 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6509 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6517 MVT VT = SVOp->getValueType(0).getSimpleVT();
6531 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6550 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6552 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6554 MVT::v32i8, &pshufbMask[0], 32));
6565 MVT VT = SVOp->getValueType(0).getSimpleVT();
6568 MVT NewVT;
6572 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6573 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6574 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6575 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6576 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6577 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6602 static SDValue getVZextMovL(MVT VT, EVT OpVT,
6605 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6612 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6613 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6618 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6644 MVT VT = SVOp->getValueType(0).getSimpleVT();
6650 MVT EltVT = VT.getVectorElementType();
6651 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6756 MVT VT = SVOp->getValueType(0).getSimpleVT();
6910 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6912 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6923 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6925 if (HasSSE2 && VT == MVT::v2f64)
6930 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6931 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6932 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6941 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
7001 assert(VT != MVT::v4i32 && "unsupported shuffle type");
7030 VT.getVectorElementType() == MVT::i64)
7100 MVT VT = Op.getValueType().getSimpleVT();
7123 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
7124 VT == MVT::v16i16 || VT == MVT::v32i8) {
7128 } else if ((VT == MVT::v4i32 ||
7129 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
7135 MVT NewVT = NewOp.getValueType().getSimpleVT();
7144 MVT NewVT = NewOp.getValueType().getSimpleVT();
7159 MVT VT = Op.getValueType().getSimpleVT();
7219 (VT == MVT::v2f64 || VT == MVT::v2i64))
7226 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
7231 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
7234 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
7255 MVT EltVT = VT.getVectorElementType();
7264 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
7267 if (VT == MVT::v4i32 || VT == MVT::v4f32)
7294 MVT EltVT = VT.getVectorElementType();
7366 if (VT == MVT::v2f64 || VT == MVT::v2i64)
7400 if (HasInt256 && VT == MVT::v8i32)
7416 if (V2IsUndef && HasInt256 && (VT == MVT::v8i32 || VT == MVT::v8f32)) {
7419 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32));
7421 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
7428 if (V2IsUndef && HasInt256 && (VT == MVT::v4i64 || VT == MVT::v4f64))
7439 if (VT == MVT::v8i16) {
7445 if (VT == MVT::v16i8) {
7451 if (VT == MVT::v32i8) {
7470 MVT VT = Op.getValueType().getSimpleVT();
7477 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7479 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7488 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7489 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7491 MVT::v4i32,
7494 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7496 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7501 if (VT == MVT::f32) {
7514 User->getValueType(0) != MVT::i32))
7516 MVT::i32,
7517 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7520 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7523 if (VT == MVT::i32 || VT == MVT::i64) {
7539 MVT VecVT = Vec.getValueType().getSimpleVT();
7557 DAG.getConstant(IdxVal, MVT::i32));
7568 MVT VT = Op.getValueType().getSimpleVT();
7574 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7575 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7577 MVT::v4i32, Vec),
7580 MVT EltVT = MVT::i32;
7595 MVT VVT = Op.getOperand(0).getValueType().getSimpleVT();
7614 MVT VVT = Op.getOperand(0).getValueType().getSimpleVT();
7625 MVT VT = Op.getValueType().getSimpleVT();
7626 MVT EltVT = VT.getVectorElementType();
7639 if (VT == MVT::v8i16)
7641 else if (VT == MVT::v16i8)
7648 if (N1.getValueType() != MVT::i32)
7649 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7650 if (N2.getValueType() != MVT::i32)
7655 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7666 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7670 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7679 MVT VT = Op.getValueType().getSimpleVT();
7680 MVT EltVT = VT.getVectorElementType();
7702 DAG.getConstant(IdxIn128, MVT::i32));
7711 if (EltVT == MVT::i8)
7717 if (N1.getValueType() != MVT::i32)
7718 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7719 if (N2.getValueType() != MVT::i32)
7729 MVT OpVT = Op.getValueType().getSimpleVT();
7746 if (OpVT == MVT::v1i64 &&
7747 Op.getOperand(0).getValueType() == MVT::i64)
7748 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7750 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7753 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
8015 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8214 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8269 IDX, MachinePointerInfo(), MVT::i32,
8309 DAG.getConstant(VTBits - 1, MVT::i8))
8321 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8322 DAG.getConstant(VTBits, MVT::i8));
8323 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8324 AndNode, DAG.getConstant(0, MVT::i8));
8327 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8350 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
8355 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
8357 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
8382 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
8384 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
8417 Tys = DAG.getVTList(MVT::Other);
8472 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8474 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8477 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8478 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8481 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8484 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8485 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8490 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8492 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8493 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8495 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8496 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8500 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8510 MVT::f64);
8513 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8519 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8520 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8524 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8525 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8527 MVT::v2f64, Load)),
8528 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8530 MVT::v2f64, Bias)));
8531 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8532 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8536 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8541 if (DestVT.bitsLT(MVT::f64))
8544 if (DestVT.bitsGT(MVT::f64))
8557 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8558 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8561 EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
8583 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8585 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8587 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8591 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8592 if (SrcVT == MVT::i32) {
8599 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8602 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8606 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8621 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8622 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8624 array_lengthof(Ops), MVT::i64, MMO);
8630 getSetCCResultType(*DAG.getContext(), MVT::i64),
8631 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8648 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8650 MVT::f32, false, false, 4);
8652 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8664 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8665 DstTy = MVT::i64;
8668 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8669 DstTy.getSimpleVT() >= MVT::i16 &&
8673 if (DstTy == MVT::i32 &&
8677 DstTy == MVT::i64 &&
8694 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8695 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8696 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8705 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8709 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8731 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8737 DAG.getVTList(MVT::Other, MVT::Glue),
8740 MVT::i32, ftol.getValue(1));
8742 MVT::i32, eax.getValue(2));
8745 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, array_lengthof(Ops))
8753 MVT VT = Op->getValueType(0).getSimpleVT();
8755 MVT InVT = In.getValueType().getSimpleVT();
8771 if (((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
8772 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
8784 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
8806 MVT VT = Op.getValueType().getSimpleVT();
8808 MVT SVT = In.getValueType().getSimpleVT();
8826 SDValue Lo = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32, In);
8828 SDValue Hi = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32,
8829 DAG.getVectorShuffle(MVT::v8i16, DL, In,
8830 DAG.getUNDEF(MVT::v8i16),
8833 return DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i32, Lo, Hi);
8838 MVT VT = Op.getValueType().getSimpleVT();
8840 MVT SVT = In.getValueType().getSimpleVT();
8842 if ((VT == MVT::v4i32) && (SVT == MVT::v4i64)) {
8846 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
8847 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
8854 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8856 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8859 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
8860 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
8873 if ((VT == MVT::v8i16) && (SVT == MVT::v8i32)) {
8876 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
8880 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
8881 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
8882 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
8883 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
8884 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
8885 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
8886 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
8887 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
8889 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
8891 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
8893 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
8894 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
8897 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
8899 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8904 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
8907 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
8910 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
8911 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
8917 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
8918 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
8919 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
8921 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
8922 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
8926 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
8927 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
8955 MVT VT = Op.getValueType().getSimpleVT();
8957 if (VT == MVT::v8i16)
8960 MVT::v8i32, Op.getOperand(0)));
8999 MVT VT = Op.getValueType().getSimpleVT();
9001 MVT SVT = In.getValueType().getSimpleVT();
9003 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
9006 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
9013 MVT VT = Op.getValueType().getSimpleVT();
9014 MVT EltVT = VT;
9015 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9021 if (EltVT == MVT::f64)
9034 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9047 MVT VT = Op.getValueType().getSimpleVT();
9048 MVT EltVT = VT;
9049 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9055 if (EltVT == MVT::f64)
9068 MVT XORVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9084 MVT VT = Op.getValueType().getSimpleVT();
9085 MVT SrcVT = Op1.getValueType().getSimpleVT();
9103 if (SrcVT == MVT::f64) {
9123 // Op0 is MVT::f32, Op1 is MVT::f64.
9124 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
9125 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
9126 DAG.getConstant(32, MVT::i32));
9127 MVT::v4f32, SignBit);
9128 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
9134 if (VT == MVT::f64) {
9161 MVT VT = Op.getValueType().getSimpleVT();
9186 EVT VT = MVT::Other;
9243 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9258 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
9290 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9460 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9463 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9482 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9483 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9485 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9490 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9509 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9510 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9511 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9512 DAG.getConstant(8, MVT::i8));
9513 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9514 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
9575 if (LHS.getValueType() == MVT::i8 ||
9576 LHS.getValueType() == MVT::i16)
9577 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9584 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
9586 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9587 DAG.getConstant(Cond, MVT::i8), BT);
9641 MVT VT = Op.getValueType().getSimpleVT();
9661 MVT EltVT = VT.getVectorElementType();
9662 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9674 MVT VT = Op.getValueType().getSimpleVT();
9681 MVT EltVT = Op0.getValueType().getVectorElementType().getSimpleVT();
9682 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
9699 DAG.getConstant(CC0, MVT::i8));
9701 DAG.getConstant(CC1, MVT::i8));
9706 DAG.getConstant(SSECC, MVT::i8));
9734 MVT VET = VT.getVectorElementType();
9736 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
9737 || (Subtarget->hasSSE2() && (VET == MVT::i8));
9754 if (VT == MVT::v2i64) {
9759 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
9760 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
9767 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
9769 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
9770 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
9771 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
9774 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
9775 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
9778 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
9779 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
9784 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
9785 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
9786 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
9788 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
9789 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
9792 Result = DAG.getNOT(dl, Result, MVT::v4i32);
9803 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
9804 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
9807 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
9811 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
9812 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
9815 Result = DAG.getNOT(dl, Result, MVT::v4i32);
9844 MVT VT = Op.getValueType().getSimpleVT();
9848 assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
9883 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9884 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
9895 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9896 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
9953 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
9954 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
9961 unsigned Opcode = VT == MVT::f32 ? X86ISD::FSETCCss : X86ISD::FSETCCsd;
9963 DAG.getConstant(SSECC, MVT::i8));
9998 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
10003 DAG.getConstant(X86::COND_B, MVT::i8),
10008 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
10014 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
10043 MVT VT = Op.getValueType().getSimpleVT();
10058 Cond.getOperand(0).getValueType() != MVT::i8)) {
10075 MVT::i32);
10077 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10086 CC = DAG.getConstant(X86Cond, MVT::i8);
10108 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10123 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
10133 if (Op.getValueType() == MVT::i8 &&
10139 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
10147 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
10154 MVT VT = Op->getValueType(0).getSimpleVT();
10156 MVT InVT = In.getValueType().getSimpleVT();
10159 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
10160 (VT != MVT::v8i32 || InVT != MVT::v8i16))
10190 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
10301 Cond.getOperand(0).getValueType() != MVT::i8)) {
10320 MVT::i32);
10322 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10331 CC = DAG.getConstant(X86Cond, MVT::i8);
10362 CC = DAG.getConstant(CCode, MVT::i8);
10380 CC = DAG.getConstant(CCode, MVT::i8);
10393 CC = DAG.getConstant(CCode, MVT::i8);
10416 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10419 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10422 CC = DAG.getConstant(X86::COND_P, MVT::i8);
10446 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10449 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10452 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
10479 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10508 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
10527 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
10540 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10581 MVT::i32),
10590 MVT::i32),
10612 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
10637 if (ArgVT == MVT::f80) {
10662 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
10663 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
10664 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
10665 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
10668 MVT::i64,
10706 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
10717 DAG.getConstant(ShiftAmt, MVT::i32));
10733 ShOps[1] = DAG.getConstant(0, MVT::i32);
10734 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
10735 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
10739 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10740 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
10846 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
10847 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10848 DAG.getConstant(X86CC, MVT::i8), Cond);
10849 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11142 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
11143 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11144 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11145 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11298 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11300 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11301 DAG.getConstant(X86CC, MVT::i8),
11303 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11315 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11407 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
11414 DAG.getConstant(X86::COND_B, MVT::i32),
11417 DAG.getVTList(Op->getValueType(1), MVT::Glue),
11427 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
11429 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11430 DAG.getConstant(X86::COND_NE, MVT::i8),
11475 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
11476 (FrameReg == X86::EBP && VT == MVT::i32)) &&
11503 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
11504 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
11507 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
11516 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
11524 DAG.getVTList(MVT::i32, MVT::Other),
11531 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
11565 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11569 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11570 DAG.getConstant(2, MVT::i64));
11578 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11579 DAG.getConstant(10, MVT::i64));
11580 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11584 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11585 DAG.getConstant(12, MVT::i64));
11592 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11593 DAG.getConstant(20, MVT::i64));
11594 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11599 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11600 DAG.getConstant(22, MVT::i64));
11601 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
11605 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
11654 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11655 DAG.getConstant(10, MVT::i32));
11656 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
11662 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
11666 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11667 DAG.getConstant(1, MVT::i32));
11673 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11674 DAG.getConstant(5, MVT::i32));
11675 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
11679 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11680 DAG.getConstant(6, MVT::i32));
11685 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
11727 DAG.getVTList(MVT::Other),
11728 Ops, array_lengthof(Ops), MVT::i16,
11732 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
11737 DAG.getNode(ISD::SRL, DL, MVT::i16,
11738 DAG.getNode(ISD::AND, DL, MVT::i16,
11739 CWD, DAG.getConstant(0x800, MVT::i16)),
11740 DAG.getConstant(11, MVT::i8));
11742 DAG.getNode(ISD::SRL, DL, MVT::i16,
11743 DAG.getNode(ISD::AND, DL, MVT::i16,
11744 CWD, DAG.getConstant(0x400, MVT::i16)),
11745 DAG.getConstant(9, MVT::i8));
11748 DAG.getNode(ISD::AND, DL, MVT::i16,
11749 DAG.getNode(ISD::ADD, DL, MVT::i16,
11750 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
11751 DAG.getConstant(1, MVT::i16)),
11752 DAG.getConstant(3, MVT::i16));
11765 if (VT == MVT::i8) {
11767 OpVT = MVT::i32;
11772 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
11779 DAG.getConstant(X86::COND_E, MVT::i8),
11787 if (VT == MVT::i8)
11788 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
11799 if (VT == MVT::i8) {
11801 OpVT = MVT::i32;
11806 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
11812 if (VT == MVT::i8)
11813 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
11824 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
11831 DAG.getConstant(X86::COND_E, MVT::i8),
11858 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11859 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
11893 if (VT == MVT::v4i32) {
11903 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
11905 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
11916 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
11930 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
11936 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
11977 SDValue Sz = DAG.getConstant(EltTy.getSizeInBits()-1, MVT::i32);
11980 SDValue Amt = DAG.getConstant(EltTy.getSizeInBits() - lg2, MVT::i32);
11983 SDValue Lg2Amt = DAG.getConstant(lg2, MVT::i32);
12011 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
12013 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
12016 DAG.getConstant(ShiftAmt, MVT::i32));
12019 DAG.getConstant(ShiftAmt, MVT::i32));
12020 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
12022 DAG.getConstant(ShiftAmt, MVT::i32));
12025 if (VT == MVT::v16i8) {
12028 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
12029 DAG.getConstant(ShiftAmt, MVT::i32));
12034 MVT::i8));
12040 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
12041 DAG.getConstant(ShiftAmt, MVT::i32));
12046 MVT::i8));
12060 MVT::i8));
12069 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
12072 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
12073 DAG.getConstant(ShiftAmt, MVT::i32));
12078 MVT::i8));
12084 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
12085 DAG.getConstant(ShiftAmt, MVT::i32));
12090 MVT::i8));
12104 MVT::i8));
12117 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
12151 DAG.getConstant(ShiftAmt, MVT::i32));
12154 DAG.getConstant(ShiftAmt, MVT::i32));
12157 DAG.getConstant(ShiftAmt, MVT::i32));
12171 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
12172 VT == MVT::v4i32 || VT == MVT::v8i16 ||
12174 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
12175 VT == MVT::v8i32 || VT == MVT::v16i16))) {
12226 if (EltVT.bitsGT(MVT::i32))
12227 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
12228 else if (EltVT.bitsLT(MVT::i32))
12229 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
12237 case MVT::v2i64:
12238 case MVT::v4i32:
12239 case MVT::v8i16:
12240 case MVT::v4i64:
12241 case MVT::v8i32:
12242 case MVT::v16i16:
12248 case MVT::v4i32:
12249 case MVT::v8i16:
12250 case MVT::v8i32:
12251 case MVT::v16i16:
12257 case MVT::v2i64:
12258 case MVT::v4i32:
12259 case MVT::v8i16:
12260 case MVT::v4i64:
12261 case MVT::v8i32:
12262 case MVT::v16i16:
12271 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
12322 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
12323 VT == MVT::v4i64 || VT == MVT::v8i32))
12326 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
12327 VT == MVT::v4i64 || VT == MVT::v8i32))
12329 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
12334 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
12338 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
12342 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
12359 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
12360 DAG.getConstant(4, MVT::i32), DAG);
12371 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
12372 DAG.getConstant(2, MVT::i32), DAG);
12390 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12391 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12480 MVT::i32);
12484 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12485 DAG.getConstant(X86::COND_O, MVT::i32),
12493 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
12498 DAG.getConstant(Cond, MVT::i32),
12515 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
12519 case MVT::v8i32:
12520 case MVT::v16i16:
12532 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12533 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12547 case MVT::v4i32:
12548 case MVT::v8i16: {
12586 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
12589 SDValue Zero = DAG.getConstant(0, MVT::i32);
12591 DAG.getRegister(X86::ESP, MVT::i32), // Base
12592 DAG.getTargetConstant(1, MVT::i8), // Scale
12593 DAG.getRegister(0, MVT::i32), // Index
12594 DAG.getTargetConstant(0, MVT::i32), // Disp
12595 DAG.getRegister(0, MVT::i32), // Segment.
12599 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
12604 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
12615 case MVT::i8: Reg = X86::AL; size = 1; break;
12616 case MVT::i16: Reg = X86::AX; size = 2; break;
12617 case MVT::i32: Reg = X86::EAX; size = 4; break;
12618 case MVT::i64:
12628 DAG.getTargetConstant(size, MVT::i8),
12630 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12642 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12646 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
12647 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
12649 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
12650 DAG.getConstant(32, MVT::i8));
12652 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
12663 assert((DstVT == MVT::i64 ||
12667 if (SrcVT==MVT::i64 && DstVT.isVector())
12669 if (DstVT==MVT::i64 && SrcVT.isVector())
12726 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
12765 bool isF64 = ArgVT == MVT::f64;
12906 assert (Node->getValueType(0) == MVT::i64 &&
12911 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
12913 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
12916 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
12918 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64,
12921 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
12966 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
12967 N->getValueType(0) != MVT::v2f32)
12969 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
12972 MVT::f64);
12973 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
12974 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
12975 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
12976 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
12977 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
12978 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
12984 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
12989 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12992 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
12994 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
12998 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops,
13005 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
13006 bool Regs64bit = T == MVT::i128;
13007 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
13033 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13365 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
13382 case MVT::i8:
13383 case MVT::i16:
13384 case MVT::i32:
13403 case MVT::f32:
13404 case MVT::f64:
13415 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
13523 case MVT::i8: return X86::LCMPXCHG8;
13524 case MVT::i16: return X86::LCMPXCHG16;
13525 case MVT::i32: return X86::LCMPXCHG32;
13526 case MVT::i64: return X86::LCMPXCHG64;
13536 case MVT::i8: return X86::MOV8rm;
13537 case MVT::i16: return X86::MOV16rm;
13538 case MVT::i32: return X86::MOV32rm;
13539 case MVT::i64: return X86::MOV64rm;
13629 case MVT::i8: return X86::CMOV_GR8;
13630 case MVT::i16: return X86::CMOV_GR16;
13631 case MVT::i32: return X86::CMOV_GR32;
13693 MVT::SimpleValueType VT = *RC->vt_begin();
13816 if (VT != MVT::i8) {
13825 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit);
13851 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
14334 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
14335 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
14767 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
14988 assert(RC->hasType(MVT::i32) && "Invalid destination!");
14994 MVT PVT = getPointerTy();
14995 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15038 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
15058 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
15115 MVT PVT = getPointerTy();
15116 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15120 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
15125 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
15133 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
15134 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
15563 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
15578 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
15765 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
15766 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
15773 if (InputVector.getValueType() != MVT::v4i32)
15790 if (Extract->getValueType(0) != MVT::i32)
15857 case MVT::v32i8:
15858 case MVT::v16i16:
15859 case MVT::v8i32:
15862 case MVT::v16i8:
15863 case MVT::v8i16:
15864 case MVT::v4i32:
15871 (Subtarget->hasSSE2() && VT == MVT::v16i8);
15873 (Subtarget->hasSSE2() && VT == MVT::v8i16);
15935 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
15937 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
16105 DAG.getConstant(ShAmt, MVT::i8));
16123 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
16125 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
16202 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
16203 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
16494 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
16496 DAG.getConstant(CC, MVT::i8), Flags };
16518 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16519 DAG.getConstant(CC, MVT::i8), Cond);
16526 DAG.getConstant(ShAmt, MVT::i8));
16535 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16536 DAG.getConstant(CC, MVT::i8), Cond);
16551 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
16553 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
16573 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16574 DAG.getConstant(CC, MVT::i8), Cond);
16627 DAG.getConstant(CC, MVT::i8), Cond };
16646 if (VT != MVT::i64)
16682 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
16689 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
16750 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
16752 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
16818 if (VT == MVT::f32 || VT == MVT::f64) {
16849 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
16855 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
16856 DAG.getConstant(x86cc, MVT::i8));
16857 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
16859 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
16860 DAG.getConstant(1, MVT::i32));
16861 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
16996 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
17028 if (VT != MVT::v2i64 && VT != MVT::v4i64)
17065 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
17067 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
17134 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
17144 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
17156 if (ShAmt0.getValueType() != MVT::i8)
17159 if (ShAmt1.getValueType() != MVT::i8)
17187 MVT::i8, ShAmt0));
17196 MVT::i8, ShAmt0));
17225 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
17229 DAG.getConstant(X86::COND_GE, MVT::i8),
17231 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
17255 if (VT != MVT::i32 && VT != MVT::i64)
17311 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
17346 MVT SclrLoadTy = MVT::i8;
17347 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
17348 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
17349 MVT Tp = (MVT::SimpleValueType)tp;
17356 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
17358 SclrLoadTy = MVT::f64;
17412 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
17508 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
17553 MVT StoreType = MVT::i8;
17554 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
17555 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
17556 MVT Tp = (MVT::SimpleValueType)tp;
17562 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
17564 StoreType = MVT::f64;
17588 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
17607 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
17647 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
17655 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
17666 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
17667 DAG.getConstant(4, MVT::i32));
17669 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
17673 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
17683 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
17688 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
17689 DAG.getConstant(4, MVT::i32));
17700 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
17735 MVT VT = LHS.getValueType().getSimpleVT();
17839 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
17840 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
17854 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
17855 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
17972 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
17982 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
17983 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
17985 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
18020 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
18115 return DAG.getNode(ISD::AND, DL, MVT::i8,
18116 MVT::i8,
18117 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
18118 DAG.getConstant(1, MVT::i8));
18157 SDValue Cond = DAG.getConstant(CC, MVT::i8);
18179 SDValue Cond = DAG.getConstant(CC, MVT::i8);
18193 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
18195 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
18234 DAG.getConstant(X86::COND_B,MVT::i8),
18270 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
18291 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
18292 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
18324 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
18325 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
18417 if (VT != MVT::i16)
18444 if (VT != MVT::i16)
18503 PVT = MVT::i32;
18835 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
18860 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
18920 MVT VT) const {
18932 if (VT == MVT::i32 || VT == MVT::f32)
18934 if (VT == MVT::i16)
18936 if (VT == MVT::i8 || VT == MVT::i1)
18938 if (VT == MVT::i64 || VT == MVT::f64)
18944 if (VT == MVT::i32 || VT == MVT::f32)
18946 if (VT == MVT::i16)
18948 if (VT == MVT::i8 || VT == MVT::i1)
18950 if (VT == MVT::i64)
18955 if (VT == MVT::i8 || VT == MVT::i1)
18957 if (VT == MVT::i16)
18959 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
18963 if (VT == MVT::i8 || VT == MVT::i1)
18965 if (VT == MVT::i16)
18967 if (VT == MVT::i32 || !Subtarget->is64Bit())
18973 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
18975 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
18990 case MVT::f32:
18991 case MVT::i32:
18993 case MVT::f64:
18994 case MVT::i64:
18997 case MVT::v16i8:
18998 case MVT::v8i16:
18999 case MVT::v4i32:
19000 case MVT::v2i64:
19001 case MVT::v4f32:
19002 case MVT::v2f64:
19005 case MVT::v32i8:
19006 case MVT::v16i16:
19007 case MVT::v8i32:
19008 case MVT::v4i64:
19009 case MVT::v8f32:
19010 case MVT::v4f64:
19012 case MVT::v8f64:
19013 case MVT::v16f32:
19014 case MVT::v16i32:
19015 case MVT::v8i64:
19077 if (VT == MVT::i8 || VT == MVT::i1) {
19090 } else if (VT == MVT::i32 || VT == MVT::f32) {
19107 } else if (VT == MVT::i64 || VT == MVT::f64) {
19139 if (VT == MVT::f32 || VT == MVT::i32)
19141 else if (VT == MVT::f64 || VT == MVT::i64)
