Lines Matching refs:SmallVectorImpl
1762 const SmallVectorImpl<ISD::OutputArg> &Outs,
1773 const SmallVectorImpl<ISD::OutputArg> &Outs,
1774 const SmallVectorImpl<SDValue> &OutVals,
1942 const SmallVectorImpl<ISD::InputArg> &Ins,
1944 SmallVectorImpl<SDValue> &InVals) const {
2016 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2031 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2093 const SmallVectorImpl<ISD::InputArg> &Ins,
2135 const SmallVectorImpl<ISD::InputArg> &Ins,
2138 SmallVectorImpl<SDValue> &InVals)
2470 SmallVectorImpl<SDValue> &InVals) const {
2473 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2474 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2475 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3025 const SmallVectorImpl<ISD::OutputArg> &Outs,
3026 const SmallVectorImpl<SDValue> &OutVals,
3027 const SmallVectorImpl<ISD::InputArg> &Ins,
3676 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4697 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4850 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5307 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
9194 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12882 SmallVectorImpl<SDValue> &Results,
12903 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
12928 SmallVectorImpl<SDValue>&Results,
13423 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
13445 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
15820 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
