Lines Matching refs:t1L
13913 // t1L = LOAD [MI.addr + 0]
13916 // t4L = phi(t1L, t3L / loop)
13971 unsigned t1L = MRI.createVirtualRegister(RC);
13986 // t1L = LOAD [MI.addr + 0]
13989 // t4L = phi(t1L / thisMBB, t3L / mainMBB)
14018 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L);
14059 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14145 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14165 // Copy ECX:EBX from t1H:t1L
