Lines Matching refs:v4f32
911 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
913 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
914 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
915 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
916 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
917 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
918 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
919 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
920 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
921 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
922 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
923 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
924 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1049 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1050 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1051 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1052 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1053 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1076 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1081 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1161 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1167 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1204 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1626 return MVT::v4f32;
1724 case MVT::v4f32: case MVT::v2f64:
1843 // If we don't have SSE2 available, convert to v4f32 so the generated
1846 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2375 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
3536 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
4646 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4744 // represented by v4f32 and then be manipulated by target suported shuffles.
4768 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4770 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
6018 // Next, we iteratively mix elements, e.g. for v4f32:
6558 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6572 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6605 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6928 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6930 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6931 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6932 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6941 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6947 // v4i32 or v4f32
6969 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
7129 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
7226 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
7231 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
7234 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
7267 if (VT == MVT::v4i32 || VT == MVT::v4f32)
7666 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
9006 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
9127 v4f32, SignBit);
12338 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
12978 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
12984 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
17839 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
17854 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
19001 case MVT::v4f32:
