Lines Matching full:opsize
788 TB, OpSize, VEX;
794 TB, OpSize, VEX;
801 TB, OpSize, VEX, VEX_L;
807 TB, OpSize, VEX, VEX_L;
813 TB, OpSize;
819 TB, OpSize;
1138 itin, SSEPackedDouble>, TB, OpSize,
2096 // SSE2 instructions without OpSize prefix
2363 "ucomisd">, TB, OpSize, VEX, VEX_LIG;
2368 "comisd">, TB, OpSize, VEX, VEX_LIG;
2374 load, "ucomisd">, TB, OpSize, VEX;
2379 load, "comisd">, TB, OpSize, VEX;
2383 "ucomisd">, TB, OpSize;
2389 "comisd">, TB, OpSize;
2395 load, "ucomisd">, TB, OpSize;
2400 "comisd">, TB, OpSize;
2437 SSEPackedDouble>, TB, OpSize, VEX_4V;
2445 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2454 SSEPackedDouble>, TB, OpSize;
2520 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2523 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2533 TB, OpSize;
2608 SSEPackedDouble>, TB, OpSize, VEX_4V;
2614 SSEPackedDouble>, TB, OpSize, VEX_4V;
2621 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2627 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2635 SSEPackedDouble>, TB, OpSize;
2641 SSEPackedDouble>, TB, OpSize;
2703 OpSize, VEX;
2709 OpSize, VEX, VEX_L;
2727 OpSize, VEX, Sched<[WriteVecLogic]>;
2734 OpSize, VEX, VEX_L, Sched<[WriteVecLogic]>;
2740 SSEPackedDouble>, TB, OpSize;
2825 TB, OpSize, VEX_4V;
2834 TB, OpSize;
2866 TB, OpSize, VEX_4V, VEX_L;
2883 TB, OpSize, VEX_4V;
2897 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2943 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_4V;
2950 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_4V, VEX_L;
2959 itins.d, 1>, TB, OpSize;
4134 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, TB, OpSize;
4287 imm:$src2))]>, TB, OpSize, VEX,
4298 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4302 []>, TB, OpSize, VEX_4V, Sched<[WriteShuffle]>;
4306 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[UseSSE2]>;
4975 f128mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
4977 f256mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V, VEX_L;
4986 f128mem, SSE_ALU_F64P>, TB, OpSize;
5073 OpSize, Sched<[WriteVecALU]>;
5081 OpSize, Sched<[WriteVecALULd]>;
5091 OpSize, Sched<[WriteVecALU]>;
5098 (bitconvert (memopv4i64 addr:$src))))]>, OpSize,
5218 OpSize, Sched<[itins.Sched]>;
5226 (bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize,
5241 OpSize, Sched<[itins.Sched]>;
5249 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize,
5260 OpSize;
5266 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
5392 [], IIC_SSE_PALIGNR>, OpSize, Sched<[WriteShuffle]>;
5400 [], IIC_SSE_PALIGNR>, OpSize, Sched<[WriteShuffleLd, ReadAfterLd]>;
5410 []>, OpSize, Sched<[WriteShuffle]>;
5416 []>, OpSize, Sched<[WriteShuffleLd, ReadAfterLd]>;
5495 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5501 OpSize;
5508 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5512 [(set VR256:$dst, (IntId (load addr:$src)))]>, OpSize;
5668 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5674 OpSize;
5681 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5687 OpSize;
5746 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5753 OpSize;
5760 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5767 OpSize;
6040 OpSize;
6046 []>, OpSize;
6056 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
6069 []>, OpSize;
6088 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
6094 addr:$dst)]>, OpSize;
6109 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
6115 addr:$dst)]>, OpSize, REX_W;
6132 OpSize;
6138 addr:$dst)]>, OpSize;
6147 []>, OpSize, VEX;
6176 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
6185 imm:$src3))]>, OpSize;
6202 OpSize;
6211 imm:$src3)))]>, OpSize;
6228 OpSize;
6237 imm:$src3)))]>, OpSize;
6258 OpSize;
6268 imm:$src3))]>, OpSize;
6294 OpSize;
6303 OpSize;
6313 OpSize;
6322 OpSize;
6340 []>, OpSize;
6351 OpSize;
6363 OpSize;
6374 []>, OpSize;
6385 OpSize;
6397 OpSize;
6544 OpSize, VEX;
6548 OpSize, VEX;
6553 OpSize, VEX, VEX_L;
6557 OpSize, VEX, VEX_L;
6564 OpSize;
6568 OpSize;
6576 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6580 OpSize, VEX;
6604 OpSize, XS;
6608 (implicit EFLAGS)]>, OpSize, XS;
6637 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6643 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6661 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
6669 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
6679 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6685 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
6699 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6707 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6813 OpSize;
6824 OpSize;
6898 NoItinerary, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6907 NoItinerary, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6997 OpSize;
7005 (bitconvert (mem_frag addr:$src2)), XMM0))]>, OpSize;
7065 OpSize, VEX;
7070 OpSize, VEX, VEX_L;
7074 OpSize;
7090 OpSize;
7097 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
7137 []>, OpSize;
7142 []>, OpSize;
7172 []>, OpSize;
7177 []>, OpSize;
7207 []>, OpSize;
7212 []>, OpSize;
7243 []>, OpSize;
7248 []>, OpSize;
7284 OpSize;
7290 OpSize;
7342 OpSize;
7349 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
7382 OpSize, VEX;
7387 OpSize, VEX;
7394 OpSize;
7399 OpSize;
7408 OpSize, VEX;
7414 OpSize, VEX;
7421 OpSize;
7427 OpSize;
7493 imm:$idx))]>, TB, OpSize;
7498 VR128:$mask))]>, TB, OpSize;
7885 T8, OpSize, VEX;
7888 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7896 TA, OpSize, VEX;
7901 TA, OpSize, VEX;
