Lines Matching defs:ISD
174 int ISD = TLI->InstructionOpcodeToISD(Opcode);
175 assert(ISD && "Invalid opcode");
180 { ISD::SHL, MVT::v4i32, 1 },
181 { ISD::SRL, MVT::v4i32, 1 },
182 { ISD::SRA, MVT::v4i32, 1 },
183 { ISD::SHL, MVT::v8i32, 1 },
184 { ISD::SRL, MVT::v8i32, 1 },
185 { ISD::SRA, MVT::v8i32, 1 },
186 { ISD::SHL, MVT::v2i64, 1 },
187 { ISD::SRL, MVT::v2i64, 1 },
188 { ISD::SHL, MVT::v4i64, 1 },
189 { ISD::SRL, MVT::v4i64, 1 },
191 { ISD::SHL, MVT::v32i8, 42 }, // cmpeqb sequence.
192 { ISD::SHL, MVT::v16i16, 16*10 }, // Scalarized.
194 { ISD::SRL, MVT::v32i8, 32*10 }, // Scalarized.
195 { ISD::SRL, MVT::v16i16, 8*10 }, // Scalarized.
197 { ISD::SRA, MVT::v32i8, 32*10 }, // Scalarized.
198 { ISD::SRA, MVT::v16i16, 16*10 }, // Scalarized.
199 { ISD::SRA, MVT::v4i64, 4*10 }, // Scalarized.
202 { ISD::SDIV, MVT::v32i8, 32*20 },
203 { ISD::SDIV, MVT::v16i16, 16*20 },
204 { ISD::SDIV, MVT::v8i32, 8*20 },
205 { ISD::SDIV, MVT::v4i64, 4*20 },
206 { ISD::UDIV, MVT::v32i8, 32*20 },
207 { ISD::UDIV, MVT::v16i16, 16*20 },
208 { ISD::UDIV, MVT::v8i32, 8*20 },
209 { ISD::UDIV, MVT::v4i64, 4*20 },
215 ISD, LT.second);
224 { ISD::SHL, MVT::v16i8, 1 }, // psllw.
225 { ISD::SHL, MVT::v8i16, 1 }, // psllw.
226 { ISD::SHL, MVT::v4i32, 1 }, // pslld
227 { ISD::SHL, MVT::v2i64, 1 }, // psllq.
229 { ISD::SRL, MVT::v16i8, 1 }, // psrlw.
230 { ISD::SRL, MVT::v8i16, 1 }, // psrlw.
231 { ISD::SRL, MVT::v4i32, 1 }, // psrld.
232 { ISD::SRL, MVT::v2i64, 1 }, // psrlq.
234 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb.
235 { ISD::SRA, MVT::v8i16, 1 }, // psraw.
236 { ISD::SRA, MVT::v4i32, 1 }, // psrad.
243 ISD, LT.second);
258 { ISD::SHL, MVT::v16i8, 30 }, // cmpeqb sequence.
259 { ISD::SHL, MVT::v8i16, 8*10 }, // Scalarized.
260 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul.
261 { ISD::SHL, MVT::v2i64, 2*10 }, // Scalarized.
263 { ISD::SRL, MVT::v16i8, 16*10 }, // Scalarized.
264 { ISD::SRL, MVT::v8i16, 8*10 }, // Scalarized.
265 { ISD::SRL, MVT::v4i32, 4*10 }, // Scalarized.
266 { ISD::SRL, MVT::v2i64, 2*10 }, // Scalarized.
268 { ISD::SRA, MVT::v16i8, 16*10 }, // Scalarized.
269 { ISD::SRA, MVT::v8i16, 8*10 }, // Scalarized.
270 { ISD::SRA, MVT::v4i32, 4*10 }, // Scalarized.
271 { ISD::SRA, MVT::v2i64, 2*10 }, // Scalarized.
279 { ISD::SDIV, MVT::v16i8, 16*20 },
280 { ISD::SDIV, MVT::v8i16, 8*20 },
281 { ISD::SDIV, MVT::v4i32, 4*20 },
282 { ISD::SDIV, MVT::v2i64, 2*20 },
283 { ISD::UDIV, MVT::v16i8, 16*20 },
284 { ISD::UDIV, MVT::v8i16, 8*20 },
285 { ISD::UDIV, MVT::v4i32, 4*20 },
286 { ISD::UDIV, MVT::v2i64, 2*20 },
291 ISD, LT.second);
300 { ISD::MUL, MVT::v8i32, 4 },
301 { ISD::SUB, MVT::v8i32, 4 },
302 { ISD::ADD, MVT::v8i32, 4 },
303 { ISD::SUB, MVT::v4i64, 4 },
304 { ISD::ADD, MVT::v4i64, 4 },
310 { ISD::MUL, MVT::v4i64, 18 },
316 ISD, LT.second);
325 { ISD::MUL, MVT::v2i64, 9 },
326 { ISD::MUL, MVT::v4i64, 9 },
329 ISD, LT.second);
335 if (ISD == ISD::MUL && LT.second == MVT::v4i32 && ST->hasSSE2() &&
360 int ISD = TLI->InstructionOpcodeToISD(Opcode);
361 assert(ISD && "Invalid opcode");
370 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
371 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
372 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
373 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
374 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
375 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
376 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
377 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
379 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
380 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 },
381 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
382 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
383 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
384 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 },
385 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
386 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
392 ISD, LTDest.second, LTSrc.second);
405 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
406 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
407 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
408 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
409 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 },
410 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 1 },
412 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 },
413 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 },
414 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
415 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 },
416 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
417 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
418 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 },
419 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
420 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 },
421 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 },
422 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 },
423 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 },
425 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 },
426 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 },
427 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
428 { ISD
429 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 },
430 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 },
431 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
432 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 },
433 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 },
434 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 },
435 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 },
436 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 },
438 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 1 },
439 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
440 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 6 },
441 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 9 },
442 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 8 },
443 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 },
444 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 },
445 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 },
451 ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT());
466 int ISD = TLI->InstructionOpcodeToISD(Opcode);
467 assert(ISD && "Invalid opcode");
470 { ISD::SETCC, MVT::v2f64, 1 },
471 { ISD::SETCC, MVT::v4f32, 1 },
472 { ISD::SETCC, MVT::v2i64, 1 },
473 { ISD::SETCC, MVT::v4i32, 1 },
474 { ISD::SETCC, MVT::v8i16, 1 },
475 { ISD::SETCC, MVT::v16i8, 1 },
479 { ISD::SETCC, MVT::v4f64, 1 },
480 { ISD::SETCC, MVT::v8f32, 1 },
482 { ISD::SETCC, MVT::v4i64, 4 },
483 { ISD::SETCC, MVT::v8i32, 4 },
484 { ISD::SETCC, MVT::v16i16, 4 },
485 { ISD::SETCC, MVT::v32i8, 4 },
489 { ISD::SETCC, MVT::v4i64, 1 },
490 { ISD::SETCC, MVT::v8i32, 1 },
491 { ISD::SETCC, MVT::v16i16, 1 },
492 { ISD::SETCC, MVT::v32i8, 1 },
497 ISD, MTy);
504 ISD, MTy);
511 ISD, MTy);
