Lines Matching full:nounwind
3 define <8 x i8> @vqshrns8(<8 x i16>* %A) nounwind {
11 define <4 x i16> @vqshrns16(<4 x i32>* %A) nounwind {
19 define <2 x i32> @vqshrns32(<2 x i64>* %A) nounwind {
27 define <8 x i8> @vqshrnu8(<8 x i16>* %A) nounwind {
35 define <4 x i16> @vqshrnu16(<4 x i32>* %A) nounwind {
43 define <2 x i32> @vqshrnu32(<2 x i64>* %A) nounwind {
51 define <8 x i8> @vqshruns8(<8 x i16>* %A) nounwind {
59 define <4 x i16> @vqshruns16(<4 x i32>* %A) nounwind {
67 define <2 x i32> @vqshruns32(<2 x i64>* %A) nounwind {
75 declare <8 x i8> @llvm.arm.neon.vqshiftns.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
76 declare <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
77 declare <2 x i32> @llvm.arm.neon.vqshiftns.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
79 declare <8 x i8> @llvm.arm.neon.vqshiftnu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
80 declare <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
81 declare <2 x i32> @llvm.arm.neon.vqshiftnu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
83 declare <8 x i8> @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
84 declare <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
85 declare <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
87 define <8 x i8> @vqrshrns8(<8 x i16>* %A) nounwind {
95 define <4 x i16> @vqrshrns16(<4 x i32>* %A) nounwind {
103 define <2 x i32> @vqrshrns32(<2 x i64>* %A) nounwind {
111 define <8 x i8> @vqrshrnu8(<8 x i16>* %A) nounwind {
119 define <4 x i16> @vqrshrnu16(<4 x i32>* %A) nounwind {
127 define <2 x i32> @vqrshrnu32(<2 x i64>* %A) nounwind {
135 define <8 x i8> @vqrshruns8(<8 x i16>* %A) nounwind {
143 define <4 x i16> @vqrshruns16(<4 x i32>* %A) nounwind {
151 define <2 x i32> @vqrshruns32(<2 x i64>* %A) nounwind {
159 declare <8 x i8> @llvm.arm.neon.vqrshiftns.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
160 declare <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
161 declare <2 x i32> @llvm.arm.neon.vqrshiftns.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
163 declare <8 x i8> @llvm.arm.neon.vqrshiftnu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
164 declare <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
165 declare <2 x i32> @llvm.arm.neon.vqrshiftnu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
167 declare <8 x i8> @llvm.arm.neon.vqrshiftnsu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
168 declare <4 x i16> @llvm.arm.neon.vqrshiftnsu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
169 declare <2 x i32> @llvm.arm.neon.vqrshiftnsu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
