Lines Matching full:nounwind
3 define i32 @test__builtin_mips_extr_w1(i32 %i0, i32, i64 %a0) nounwind {
11 declare i32 @llvm.mips.extr.w(i64, i32) nounwind
13 define i32 @test__builtin_mips_extr_w2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
21 define i32 @test__builtin_mips_extr_r_w1(i32 %i0, i32, i64 %a0) nounwind {
29 declare i32 @llvm.mips.extr.r.w(i64, i32) nounwind
31 define i32 @test__builtin_mips_extr_s_h1(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
39 declare i32 @llvm.mips.extr.s.h(i64, i32) nounwind
41 define i32 @test__builtin_mips_extr_rs_w1(i32 %i0, i32, i64 %a0) nounwind {
49 declare i32 @llvm.mips.extr.rs.w(i64, i32) nounwind
51 define i32 @test__builtin_mips_extr_rs_w2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
59 define i32 @test__builtin_mips_extr_s_h2(i32 %i0, i32, i64 %a0) nounwind {
67 define i32 @test__builtin_mips_extr_r_w2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
75 define i32 @test__builtin_mips_extp1(i32 %i0, i32, i64 %a0) nounwind {
83 declare i32 @llvm.mips.extp(i64, i32) nounwind
85 define i32 @test__builtin_mips_extp2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
93 define i32 @test__builtin_mips_extpdp1(i32 %i0, i32, i64 %a0) nounwind {
101 declare i32 @llvm.mips.extpdp(i64, i32) nounwind
103 define i32 @test__builtin_mips_extpdp2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
111 define i64 @test__builtin_mips_dpau_h_qbl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
121 declare i64 @llvm.mips.dpau.h.qbl(i64, <4 x i8>, <4 x i8>) nounwind readnone
123 define i64 @test__builtin_mips_dpau_h_qbr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
133 declare i64 @llvm.mips.dpau.h.qbr(i64, <4 x i8>, <4 x i8>) nounwind readnone
135 define i64 @test__builtin_mips_dpsu_h_qbl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
145 declare i64 @llvm.mips.dpsu.h.qbl(i64, <4 x i8>, <4 x i8>) nounwind readnone
147 define i64 @test__builtin_mips_dpsu_h_qbr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind readnone {
157 declare i64 @llvm.mips.dpsu.h.qbr(i64, <4 x i8>, <4 x i8>) nounwind readnone
159 define i64 @test__builtin_mips_dpaq_s_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
169 declare i64 @llvm.mips.dpaq.s.w.ph(i64, <2 x i16>, <2 x i16>) nounwind
171 define i64 @test__builtin_mips_dpaq_sa_l_w1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind {
179 declare i64 @llvm.mips.dpaq.sa.l.w(i64, i32, i32) nounwind
181 define i64 @test__builtin_mips_dpsq_s_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
191 declare i64 @llvm.mips.dpsq.s.w.ph(i64, <2 x i16>, <2 x i16>) nounwind
193 define i64 @test__builtin_mips_dpsq_sa_l_w1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind {
201 declare i64 @llvm.mips.dpsq.sa.l.w(i64, i32, i32) nounwind
203 define i64 @test__builtin_mips_mulsaq_s_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
213 declare i64 @llvm.mips.mulsaq.s.w.ph(i64, <2 x i16>, <2 x i16>) nounwind
215 define i64 @test__builtin_mips_maq_s_w_phl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
225 declare i64 @llvm.mips.maq.s.w.phl(i64, <2 x i16>, <2 x i16>) nounwind
227 define i64 @test__builtin_mips_maq_s_w_phr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
237 declare i64 @llvm.mips.maq.s.w.phr(i64, <2 x i16>, <2 x i16>) nounwind
239 define i64 @test__builtin_mips_maq_sa_w_phl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
249 declare i64 @llvm.mips.maq.sa.w.phl(i64, <2 x i16>, <2 x i16>) nounwind
251 define i64 @test__builtin_mips_maq_sa_w_phr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nounwind {
261 declare i64 @llvm.mips.maq.sa.w.phr(i64, <2 x i16>, <2 x i16>) nounwind
263 define i64 @test__builtin_mips_shilo1(i32 %i0, i32, i64 %a0) nounwind readnone {
271 declare i64 @llvm.mips.shilo(i64, i32) nounwind readnone
273 define i64 @test__builtin_mips_shilo2(i32 %i0, i32, i64 %a0, i32 %a1) nounwind readnone {
281 define i64 @test__builtin_mips_mthlip1(i32 %i0, i32, i64 %a0, i32 %a1) nounwind {
289 declare i64 @llvm.mips.mthlip(i64, i32) nounwind
291 define i32 @test__builtin_mips_bposge321(i32 %i0) nounwind readonly {
299 declare i32 @llvm.mips.bposge32() nounwind readonly
301 define i64 @test__builtin_mips_madd1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone {
309 declare i64 @llvm.mips.madd(i64, i32, i32) nounwind readnone
311 define i64 @test__builtin_mips_maddu1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone {
319 declare i64 @llvm.mips.maddu(i64, i32, i32) nounwind readnone
321 define i64 @test__builtin_mips_msub1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone {
329 declare i64 @llvm.mips.msub(i64, i32, i32) nounwind readnone
331 define i64 @test__builtin_mips_msubu1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone {
339 declare i64 @llvm.mips.msubu(i64, i32, i32) nounwind readnone
341 define i64 @test__builtin_mips_mult1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
349 declare i64 @llvm.mips.mult(i32, i32) nounwind readnone
351 define i64 @test__builtin_mips_multu1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
359 declare i64 @llvm.mips.multu(i32, i32) nounwind readnone
361 define { i32 } @test__builtin_mips_addq_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
373 declare <2 x i16> @llvm.mips.addq.ph(<2 x i16>, <2 x i16>) nounwind
375 define { i32 } @test__builtin_mips_addq_s_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
387 declare <2 x i16> @llvm.mips.addq.s.ph(<2 x i16>, <2 x i16>) nounwind
389 define i32 @test__builtin_mips_addq_s_w1(i32 %i0, i32 %a0, i32 %a1) nounwind {
397 declare i32 @llvm.mips.addq.s.w(i32, i32) nounwind
399 define { i32 } @test__builtin_mips_addu_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
411 declare <4 x i8> @llvm.mips.addu.qb(<4 x i8>, <4 x i8>) nounwind
413 define { i32 } @test__builtin_mips_addu_s_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
425 declare <4 x i8> @llvm.mips.addu.s.qb(<4 x i8>, <4 x i8>) nounwind
427 define { i32 } @test__builtin_mips_subq_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
439 declare <2 x i16> @llvm.mips.subq.ph(<2 x i16>, <2 x i16>) nounwind
441 define { i32 } @test__builtin_mips_subq_s_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
453 declare <2 x i16> @llvm.mips.subq.s.ph(<2 x i16>, <2 x i16>) nounwind
455 define i32 @test__builtin_mips_subq_s_w1(i32 %i0, i32 %a0, i32 %a1) nounwind {
463 declare i32 @llvm.mips.subq.s.w(i32, i32) nounwind
465 define { i32 } @test__builtin_mips_subu_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
477 declare <4 x i8> @llvm.mips.subu.qb(<4 x i8>, <4 x i8>) nounwind
479 define { i32 } @test__builtin_mips_subu_s_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
491 declare <4 x i8> @llvm.mips.subu.s.qb(<4 x i8>, <4 x i8>) nounwind
493 define i32 @test__builtin_mips_addsc1(i32 %i0, i32 %a0, i32 %a1) nounwind {
501 declare i32 @llvm.mips.addsc(i32, i32) nounwind
503 define i32 @test__builtin_mips_addwc1(i32 %i0, i32 %a0, i32 %a1) nounwind {
511 declare i32 @llvm.mips.addwc(i32, i32) nounwind
513 define i32 @test__builtin_mips_modsub1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
521 declare i32 @llvm.mips.modsub(i32, i32) nounwind readnone
523 define i32 @test__builtin_mips_raddu_w_qb1(i32 %i0, i32 %a0.coerce) nounwind readnone {
532 declare i32 @llvm.mips.raddu.w.qb(<4 x i8>) nounwind readnone
534 define { i32 } @test__builtin_mips_muleu_s_ph_qbl1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
546 declare <2 x i16> @llvm.mips.muleu.s.ph.qbl(<4 x i8>, <2 x i16>) nounwind
548 define { i32 } @test__builtin_mips_muleu_s_ph_qbr1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
560 declare <2 x i16> @llvm.mips.muleu.s.ph.qbr(<4 x i8>, <2 x i16>) nounwind
562 define { i32 } @test__builtin_mips_mulq_rs_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
574 declare <2 x i16> @llvm.mips.mulq.rs.ph(<2 x i16>, <2 x i16>) nounwind
576 define i32 @test__builtin_mips_muleq_s_w_phl1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
586 declare i32 @llvm.mips.muleq.s.w.phl(<2 x i16>, <2 x i16>) nounwind
588 define i32 @test__builtin_mips_muleq_s_w_phr1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
598 declare i32 @llvm.mips.muleq.s.w.phr(<2 x i16>, <2 x i16>) nounwind
600 define { i32 } @test__builtin_mips_precrq_qb_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {
612 declare <4 x i8> @llvm.mips.precrq.qb.ph(<2 x i16>, <2 x i16>) nounwind readnone
614 define { i32 } @test__builtin_mips_precrq_ph_w1(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
624 declare <2 x i16> @llvm.mips.precrq.ph.w(i32, i32) nounwind readnone
626 define { i32 } @test__builtin_mips_precrq_rs_ph_w1(i32 %i0, i32 %a0, i32 %a1) nounwind {
636 declare <2 x i16> @llvm.mips.precrq.rs.ph.w(i32, i32) nounwind
638 define { i32 } @test__builtin_mips_precrqu_s_qb_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
650 declare <4 x i8> @llvm.mips.precrqu.s.qb.ph(<2 x i16>, <2 x i16>) nounwind
653 define i32 @test__builtin_mips_cmpu_eq_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
664 declare void @llvm.mips.cmpu.eq.qb(<4 x i8>, <4 x i8>) nounwind
666 declare i32 @llvm.mips.rddsp(i32) nounwind readonly
668 define i32 @test__builtin_mips_cmpu_lt_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
679 declare void @llvm.mips.cmpu.lt.qb(<4 x i8>, <4 x i8>) nounwind
681 define i32 @test__builtin_mips_cmpu_le_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
692 declare void @llvm.mips.cmpu.le.qb(<4 x i8>, <4 x i8>) nounwind
694 define i32 @test__builtin_mips_cmpgu_eq_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
704 declare i32 @llvm.mips.cmpgu.eq.qb(<4 x i8>, <4 x i8>) nounwind
706 define i32 @test__builtin_mips_cmpgu_lt_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
716 declare i32 @llvm.mips.cmpgu.lt.qb(<4 x i8>, <4 x i8>) nounwind
718 define i32 @test__builtin_mips_cmpgu_le_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
728 declare i32 @llvm.mips.cmpgu.le.qb(<4 x i8>, <4 x i8>) nounwind
730 define i32 @test__builtin_mips_cmp_eq_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
741 declare void @llvm.mips.cmp.eq.ph(<2 x i16>, <2 x i16>) nounwind
743 define i32 @test__builtin_mips_cmp_lt_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
754 declare void @llvm.mips.cmp.lt.ph(<2 x i16>, <2 x i16>) nounwind
756 define i32 @test__builtin_mips_cmp_le_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind {
767 declare void @llvm.mips.cmp.le.ph(<2 x i16>, <2 x i16>) nounwind
769 define { i32 } @test__builtin_mips_pick_qb1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readonly {
782 declare <4 x i8> @llvm.mips.pick.qb(<4 x i8>, <4 x i8>) nounwind readonly
784 define { i32 } @test__builtin_mips_pick_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readonly {
797 declare <2 x i16> @llvm.mips.pick.ph(<2 x i16>, <2 x i16>) nounwind readonly
799 define { i32 } @test__builtin_mips_packrl_ph1(i32 %i0, i32 %a0.coerce, i32 %a1.coerce) nounwind readnone {
811 declare <2 x i16> @llvm.mips.packrl.ph(<2 x i16>, <2 x i16>) nounwind readnone
813 define { i32 } @test__builtin_mips_shll_qb1(i32 %i0, i32 %a0.coerce) nounwind {
824 declare <4 x i8> @llvm.mips.shll.qb(<4 x i8>, i32) nounwind
826 define { i32 } @test__builtin_mips_shll_qb2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind {
837 define { i32 } @test__builtin_mips_shll_ph1(i32 %i0, i32 %a0.coerce) nounwind {
848 declare <2 x i16> @llvm.mips.shll.ph(<2 x i16>, i32) nounwind
850 define { i32 } @test__builtin_mips_shll_ph2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind {
861 define { i32 } @test__builtin_mips_shll_s_ph1(i32 %i0, i32 %a0.coerce) nounwind {
872 declare <2 x i16> @llvm.mips.shll.s.ph(<2 x i16>, i32) nounwind
874 define { i32 } @test__builtin_mips_shll_s_ph2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind {
885 define i32 @test__builtin_mips_shll_s_w1(i32 %i0, i32 %a0) nounwind {
893 declare i32 @llvm.mips.shll.s.w(i32, i32) nounwind
895 define i32 @test__builtin_mips_shll_s_w2(i32 %i0, i32 %a0, i32 %a1) nounwind {
903 define { i32 } @test__builtin_mips_shrl_qb1(i32 %i0, i32 %a0.coerce) nounwind readnone {
914 declare <4 x i8> @llvm.mips.shrl.qb(<4 x i8>, i32) nounwind readnone
916 define { i32 } @test__builtin_mips_shrl_qb2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind readnone {
927 define { i32 } @test__builtin_mips_shra_ph1(i32 %i0, i32 %a0.coerce) nounwind readnone {
938 declare <2 x i16> @llvm.mips.shra.ph(<2 x i16>, i32) nounwind readnone
940 define { i32 } @test__builtin_mips_shra_ph2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind readnone {
951 define { i32 } @test__builtin_mips_shra_r_ph1(i32 %i0, i32 %a0.coerce) nounwind readnone {
962 declare <2 x i16> @llvm.mips.shra.r.ph(<2 x i16>, i32) nounwind readnone
964 define { i32 } @test__builtin_mips_shra_r_ph2(i32 %i0, i32 %a0.coerce, i32 %a1) nounwind readnone {
975 define i32 @test__builtin_mips_shra_r_w1(i32 %i0, i32 %a0) nounwind readnone {
983 declare i32 @llvm.mips.shra.r.w(i32, i32) nounwind readnone
985 define i32 @test__builtin_mips_shra_r_w2(i32 %i0, i32 %a0, i32 %a1) nounwind readnone {
993 define { i32 } @test__builtin_mips_absq_s_ph1(i32 %i0, i32 %a0.coerce) nounwind {
1004 declare <2 x i16> @llvm.mips.absq.s.ph(<2 x i16>) nounwind
1006 define i32 @test__builtin_mips_absq_s_w1(i32 %i0, i32 %a0) nounwind {
1014 declare i32 @llvm.mips.absq.s.w(i32) nounwind
1016 define i32 @test__builtin_mips_preceq_w_phl1(i32 %i0, i32 %a0.coerce) nounwind readnone {
1025 declare i32 @llvm.mips.preceq.w.phl(<2 x i16>) nounwind readnone
1027 define i32 @test__builtin_mips_preceq_w_phr1(i32 %i0, i32 %a0.coerce) nounwind readnone {
1036 declare i32 @llvm.mips.preceq.w.phr(<2 x i16>) nounwind readnone
1038 define { i32 } @test__builtin_mips_precequ_ph_qbl1(i32 %i0, i32 %a0.coerce) nounwind readnone {
1049 declare <2 x i16> @llvm.mips.precequ.ph.qbl(<4 x i8>) nounwind readnone
1051 define { i32 } @test__builtin_mips_precequ_ph_qbr1(i32 %i0, i32 %a0.coerce) nounwind readnone {
1062 declare <2 x i16> @llvm.mips.precequ.ph.qbr(<4 x i8>) nounwind readnone
1064 define { i32 } @test__builtin_mips_precequ_ph_qbla1(i32 %i0, i32 %a0.coerce) nounwind readnone {
1075 declare <2 x i16> @llvm.mips.precequ.ph.qbla(<4 x i8>) nounwind readnone
1077 define { i32 } @test__builtin_mips_precequ_ph_qbra1(i32 %i0, i32 %a0.coerce) nounwind readnone {
1088 declare <2 x i16> @llvm.mips.precequ.ph.qbra(<4 x i8>) nounwind readnone
1090 define { i32 } @test__builtin_mips_preceu_ph_qbl1(i32 %i0, i32 %a0.coerce) nounwind
1101 declare <2 x i16> @llvm.mips.preceu.ph.qbl(<4 x i8>) nounwind readnone
1103 define { i32 } @test__builtin_mips_preceu_ph_qbr1(i32 %i0, i32 %a0.coerce) nounwind readnone {
1114 declare <2 x i16> @llvm.mips.preceu.ph.qbr(<4 x i8>) nounwind readnone
1116 define { i32 } @test__builtin_mips_preceu_ph_qbla1(i32 %i0, i32 %a0.coerce) nounwind readnone {
1127 declare <2 x i16> @llvm.mips.preceu.ph.qbla(<4 x i8>) nounwind readnone
1129 define { i32 } @test__builtin_mips_preceu_ph_qbra1(i32 %i0, i32 %a0.coerce) nounwind readnone {
1140 declare <2 x i16> @llvm.mips.preceu.ph.qbra(<4 x i8>) nounwind readnone
1142 define { i32 } @test__builtin_mips_repl_qb1(i32 %i0) nounwind readnone {
1152 declare <4 x i8> @llvm.mips.repl.qb(i32) nounwind readnone
1154 define { i32 } @test__builtin_mips_repl_qb2(i32 %i0, i32 %a0) nounwind readnone {
1164 define { i32 } @test__builtin_mips_repl_ph1(i32 %i0) nounwind readnone {
1174 declare <2 x i16> @llvm.mips.repl.ph(i32) nounwind readnone
1176 define { i32 } @test__builtin_mips_repl_ph2(i32 %i0, i32 %a0) nounwind readnone {
1186 define i32 @test__builtin_mips_bitrev1(i32 %i0, i32 %a0) nounwind readnone {
1194 declare i32 @llvm.mips.bitrev(i32) nounwind readnone
1196 define i32 @test__builtin_mips_lbux1(i32 %i0, i8* %a0, i32 %a1) nounwind readonly {
1204 declare i32 @llvm.mips.lbux(i8*, i32) nounwind readonly
1206 define i32 @test__builtin_mips_lhx1(i32 %i0, i8* %a0, i32 %a1) nounwind readonly {
1214 declare i32 @llvm.mips.lhx(i8*, i32) nounwind readonly
1216 define i32 @test__builtin_mips_lwx1(i32 %i0, i8* %a0, i32 %a1) nounwind readonly {
1224 declare i32 @llvm.mips.lwx(i8*, i32) nounwind readonly
1226 define i32 @test__builtin_mips_wrdsp1(i32 %i0, i32 %a0) nounwind {
1236 declare void @llvm.mips.wrdsp(i32, i32) nounwind
