Lines Matching full:nounwind
6 define <4 x i32> @pinsrd_1(i32 %s, <4 x i32> %tmp) nounwind {
16 define <16 x i8> @pinsrb_1(i8 %s, <16 x i8> %tmp) nounwind {
27 define <2 x i64> @pmovsxbd_1(i32* %p) nounwind {
35 %6 = tail call <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8> %5) nounwind readnone
47 define <2 x i64> @pmovsxwd_1(i64* %p) nounwind readonly {
52 %2 = tail call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %1) nounwind readnone ; <<4 x i32>> [#uses=1]
67 define <2 x i64> @pmovzxbq_1() nounwind {
72 %3 = tail call <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8> %2) nounwind readnone ; <<2 x i64>> [#uses=1]
84 declare <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8>) nounwind readnone
85 declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone
86 declare <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8>) nounwind readnone
91 define i32 @extractps_1(<4 x float> %v) nounwind {
102 define i32 @extractps_2(<4 x float> %v) nounwind {
119 define float @ext_1(<4 x float> %v) nounwind {
132 define float @ext_2(<4 x float> %v) nounwind {
142 define i32 @ext_3(<4 x i32> %v) nounwind {
153 define <4 x float> @insertps_1(<4 x float> %t1, <4 x float> %t2) nounwind {
154 %tmp1 = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %t1, <4 x float> %t2, i32 1) nounwind readnone
163 declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i32) nounwind readnone
165 define <4 x float> @insertps_2(<4 x float> %t1, float %t2) nounwind {
175 define <4 x float> @insertps_3(<4 x float> %t1, <4 x float> %t2) nounwind {
186 define i32 @ptestz_1(<2 x i64> %t1, <2 x i64> %t2) nounwind {
187 %tmp1 = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %t1, <2 x i64> %t2) nounwind readnone
198 define i32 @ptestz_2(<2 x i64> %t1, <2 x i64> %t2) nounwind {
199 %tmp1 = call i32 @llvm.x86.sse41.ptestc(<2 x i64> %t1, <2 x i64> %t2) nounwind readnone
210 define i32 @ptestz_3(<2 x i64> %t1, <2 x i64> %t2) nounwind {
211 %tmp1 = call i32 @llvm.x86.sse41.ptestnzc(<2 x i64> %t1, <2 x i64> %t2) nounwind readnone
223 declare i32 @llvm.x86.sse41.ptestz(<2 x i64>, <2 x i64>) nounwind readnone
224 declare i32 @llvm.x86.sse41.ptestc(<2 x i64>, <2 x i64>) nounwind readnone
225 declare i32 @llvm.x86.sse41.ptestnzc(<2 x i64>, <2 x i64>) nounwind readnone
229 define <2 x float> @buildvector(<2 x float> %A, <2 x float> %B) nounwind {
