Lines Matching defs:Processor
34 // Each processor has a SchedClassDesc table with an entry for each SchedClass.
239 // Gather and sort processor information
241 Records.getAllDerivedDefinitions("Processor");
244 // Begin processor table
249 // For each processor
251 // Next processor
252 Record *Processor = ProcessorList[i];
254 const std::string &Name = Processor->getValueAsString("Name");
256 Processor->getValueAsListOfDefs("Features");
261 << "\"Select the " << Name << " processor\", ";
281 // End processor table
382 // Multiple processor models may share an itinerary record. Emit it once.
447 // If this processor defines no itineraries, then leave the itinerary list
549 // EmitProcessorData - Generate data for processor itineraries that were
551 // Itineraries for each processor. The Itinerary lists are indexed on
558 // Multiple processor models may share an itinerary record. Emit it once.
561 // For each processor's machine model
571 // Get processor itinerary name
574 // Get the itinerary list for the processor.
585 // Begin processor itinerary table
602 // End processor itinerary table
609 // value defined in the C++ header. The Record is null if the processor does not
669 // Find the WriteRes Record that defines processor resources for this
675 // specifies a set of processor resources.
691 "defined for processor " + ProcModel.ModelName +
698 // Check this processor's list of write resources.
708 "SchedWrite and its alias on processor " +
714 // TODO: If ProcModel has a base model (previous generation processor),
718 std::string("Processor does not define resources for ")
724 /// Find the ReadAdvance record for the given SchedRead on this processor or
732 // Check this processor's list of aliases for SchedRead.
745 "defined for processor " + ProcModel.ModelName +
752 // Check this processor's ReadAdvanceList.
762 "SchedRead and its alias on processor " +
768 // TODO: If ProcModel has a base model (previous generation processor),
772 std::string("Processor does not define resources for ")
778 // Expand an explicit list of processor resources into a full list of implied
797 PrintFatalError(SubDef->getLoc(), "Processor resource group "
828 // Generate the SchedClass table for this processor and update global
829 // tables. Must be called for each processor in order.
872 // Determine if the SchedClass is actually reachable on this processor. If
873 // not don't try to locate the processor resources, it will fail.
904 // Check this processor's itinerary class resources.
1138 // Emit a SchedClass table for each processor.
1183 // For each processor model.
1186 // Emit processor resource table.
1193 // Begin processor itinerary properties
1201 OS << " " << PI->Index << ", // Processor ID\n";
1221 // Gather and sort processor information
1223 Records.getAllDerivedDefinitions("Processor");
1226 // Begin processor table
1232 // For each processor
1234 // Next processor
1235 Record *Processor = ProcessorList[i];
1237 const std::string &Name = Processor->getValueAsString("Name");
1239 SchedModels.getModelForProc(Processor).ModelName;
1250 // End processor table
1283 // Emit the processor machine model
1285 // Emit the processor lookup data
