Lines Matching refs:INDEX
477 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
536 print_temp(const struct tgsi_exec_machine *mach, uint index)
538 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
540 debug_printf("Temp[%u] =\n", index);
599 ((inst->Src[i].Register.Index ==
600 inst->Dst[0].Register.Index) ||
1048 const union tgsi_exec_channel *index,
1062 if (index->i[i] < 0) {
1068 const int pos = index->i[i] * 4 + swizzle;
1075 debug_printf("TGSI Exec: const buffer index %d"
1091 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1092 index2D->i[i], index->i[i]);
1094 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1106 chan->u[i] = mach->SystemValue[index->i[i]].u[i];
1112 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1115 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1121 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1125 mach->TempArray[index2D->i[i]][index->i[i]].xyzw[swizzle].u[i];
1131 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1134 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1142 chan->f[i] = mach->ImmArray[index->i[i]][swizzle];
1148 assert(index->i[i] >= 0);
1151 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1157 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1167 assert(index->i[i] >= 0);
1170 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1189 union tgsi_exec_channel index;
1193 /* We start with a direct index into a register file.
1198 * [1] = Register.Index
1200 index.i[0] =
1201 index.i[1] =
1202 index.i[2] =
1203 index.i[3] = reg->Register.Index;
1206 * a register file. The direct index now becomes an offset
1212 * [2] = Indirect.Index
1225 index2.i[3] = reg->Indirect.Index;
1238 index.i[0] += indir_index.i[0];
1239 index.i[1] += indir_index.i[1];
1240 index.i[2] += indir_index.i[2];
1241 index.i[3] += indir_index.i[3];
1243 /* for disabled execution channels, zero-out the index to
1248 index.i[i] = 0;
1258 * [3] = Dimension.Index
1264 index2D.i[3] = reg->Dimension.Index;
1266 /* Again, the second subscript index can be addressed indirectly
1274 * [4] = DimIndirect.Index
1286 index2.i[3] = reg->DimIndirect.Index;
1302 /* for disabled execution channels, zero-out the index to
1328 &index,
1363 int index;
1371 * a register file. The direct index now becomes an offset
1377 * [2] = Indirect.Index
1381 union tgsi_exec_channel index;
1386 index.i[0] =
1387 index.i[1] =
1388 index.i[2] =
1389 index.i[3] = reg->Indirect.Index;
1399 &index,
1413 * [3] = Dimension.Index
1419 index2D.i[3] = reg->Dimension.Index;
1421 /* Again, the second subscript index can be addressed indirectly
1429 * [4] = DimIndirect.Index
1442 index2.i[3] = reg->DimIndirect.Index;
1458 /* for disabled execution channels, zero-out the index to
1485 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1486 + reg->Register.Index;
1487 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1490 fprintf(stderr, "STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1500 index = reg->Register.Index;
1501 assert( index < TGSI_EXEC_NUM_TEMPS );
1502 dst = &mach->Temps[offset + index].xyzw[chan_index];
1506 index = reg->Register.Index;
1507 assert( index < TGSI_EXEC_NUM_TEMPS );
1512 dst = &mach->TempArray[index2D.i[0]][offset + index].xyzw[chan_index];
1516 index = reg->Register.Index;
1517 dst = &mach->Addrs[index].xyzw[chan_index];
1521 index = reg->Register.Index;
1522 assert(index < TGSI_EXEC_NUM_PREDS);
1523 dst = &mach->Predicates[index].xyzw[chan_index];
1553 assert(inst->Predicate.Index == 0);
1555 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1608 #define FETCH(VAL,INDEX,CHAN)\
1609 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1611 #define IFETCH(VAL,INDEX,CHAN)\
1612 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1753 const uint unit = inst->Src[1].Register.Index;
1918 const uint unit = inst->Src[3].Register.Index;
1999 const uint unit = inst->Src[2].Register.Index;
2008 union tgsi_exec_channel index;
2009 index.i[0] = index.i[1] = index.i[2] = index.i[3] = inst->TexOffsets[0].Index;
2011 inst->TexOffsets[0].SwizzleX, &index, &ZeroVec, &offset[0]);
2013 inst->TexOffsets[0].SwizzleY, &index, &ZeroVec, &offset[1]);
2015 inst->TexOffsets[0].SwizzleZ, &index, &ZeroVec, &offset[2]);
2070 const uint unit = inst->Src[1].Register.Index;
2100 const uint resource_unit = inst->Src[1].Register.Index;
2101 const uint sampler_unit = inst->Src[2].Register.Index;
2210 const uint resource_unit = inst->Src[1].Register.Index;
2211 const uint sampler_unit = inst->Src[2].Register.Index;
2364 assert(decl->Semantic.Index == 0);
