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79 #define NV30_VP_INST_COND_SWZ_X_MASK        (0x03 <<  9)
81 #define NV30_VP_INST_COND_SWZ_Y_MASK (0x03 << 7)
83 #define NV30_VP_INST_COND_SWZ_Z_MASK (0x03 << 5)
85 #define NV30_VP_INST_COND_SWZ_W_MASK (0x03 << 3)
89 #define NV30_VP_INST_ADDR_SWZ_MASK (0x03 << 1)
157 #define NV30_VP_SRC_REG_SWZ_X_MASK (0x03 <<12)
159 #define NV30_VP_SRC_REG_SWZ_Y_MASK (0x03 <<10)
161 #define NV30_VP_SRC_REG_SWZ_Z_MASK (0x03 << 8)
163 #define NV30_VP_SRC_REG_SWZ_W_MASK (0x03 << 6)
169 #define NV30_VP_SRC_REG_TYPE_MASK (0x03 << 0)