Lines Matching defs:tic
63 uint32_t *tic;
84 tic = &view->tic[0];
88 tic[0] = nvc0_format_table[view->pipe.format].tic;
92 swz[0] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_r, tex_int);
93 swz[1] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_g, tex_int);
94 swz[2] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_b, tex_int);
95 swz[3] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_a, tex_int);
96 tic[0] = (tic[0] & ~NV50_TIC_0_SWIZZLE__MASK) |
104 tic[2] = 0x10001000 | NV50_TIC_2_NO_BORDER;
107 tic[2] |= NV50_TIC_2_COLORSPACE_SRGB;
114 tic[2] |= NV50_TIC_2_LINEAR | NV50_TIC_2_TARGET_BUFFER;
115 tic[3] = 0;
116 tic[4] = /* width */
118 tic[5] = 0;
121 tic[2] |= NV50_TIC_2_LINEAR | NV50_TIC_2_TARGET_RECT;
123 tic[2] |= NV50_TIC_2_NORMALIZED_COORDS;
124 tic[3] = mt->level[0].pitch;
125 tic[4] = mt->base.base.width0;
126 tic[5] = (1 << 16) | mt->base.base.height0;
128 tic[6] =
129 tic[7] = 0;
130 tic[1] = address;
131 tic[2] |= address >> 32;
136 tic[2] |= NV50_TIC_2_NORMALIZED_COORDS;
138 tic[2] |=
145 /* there doesn't seem to be a base layer field in TIC */
149 tic[1] = address;
150 tic[2] |= address >> 32;
154 tic[2] |= NV50_TIC_2_TARGET_1D;
158 tic[2] |= NV50_TIC_2_TARGET_2D;
161 tic[2] |= NV50_TIC_2_TARGET_RECT;
164 tic[2] |= NV50_TIC_2_TARGET_3D;
169 tic[2] |= NV50_TIC_2_TARGET_CUBE_ARRAY;
171 tic[2] |= NV50_TIC_2_TARGET_CUBE;
174 tic[2] |= NV50_TIC_2_TARGET_1D_ARRAY;
178 tic[2] |= NV50_TIC_2_TARGET_2D_ARRAY;
186 tic[3] = mt->base.base.width0;
188 tic[3] = 0x00300000;
190 tic[4] = (1 << 31) | (mt->base.base.width0 << mt->ms_x);
192 tic[5] = (mt->base.base.height0 << mt->ms_y) & 0xffff;
193 tic[5] |= depth << 16;
194 tic[5] |= mt->base.base.last_level << 28;
196 tic[6] = (mt->ms_x > 1) ? 0x88000000 : 0x03000000; /* sampling points */
198 tic[7] = (view->pipe.u.tex.last_level << 4) | view->pipe.u.tex.first_level;
203 tic[7] |= mt->ms_mode << 12;
220 struct nv50_tic_entry *tic = nv50_tic_entry(nvc0->textures[s][i]);
224 if (!tic) {
229 res = nv04_resource(tic->pipe.texture);
231 if (tic->id < 0) {
232 tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
236 PUSH_DATAh(push, txc->offset + (tic->id * 32));
237 PUSH_DATA (push, txc->offset + (tic->id * 32));
244 PUSH_DATAp(push, &tic->tic[0], 8);
250 PUSH_DATA (push, (tic->id << 4) | 1);
252 nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
259 commands[n++] = (tic->id << 9) | (i << 1) | 1;
286 struct nv50_tic_entry *tic = nv50_tic_entry(nvc0->textures[s][i]);
290 if (!tic) {
294 res = nv04_resource(tic->pipe.texture);
296 if (tic->id < 0) {
297 tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
301 PUSH_DATAh(push, txc->offset + (tic->id * 32));
302 PUSH_DATA (push, txc->offset + (tic->id * 32));
308 PUSH_DATAp(push, &tic->tic[0], 8);
314 PUSH_DATA (push, (tic->id << 4) | 1);
316 nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
322 nvc0->tex_handles[s][i] |= tic->id;
