Lines Matching defs:cs
1903 struct radeon_winsys_cs *cs = rctx->cs;
1908 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1909 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1913 r600_write_value(cs, 0xf | (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
1918 struct radeon_winsys_cs *cs = rctx->cs;
1944 r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1945 r600_write_value(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
1946 r600_write_value(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
1947 r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1955 struct radeon_winsys_cs *cs = rctx->cs;
1972 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1973 r600_write_value(cs, (resource_offset + buffer_index) * 8);
1974 r600_write_value(cs
1975 r600_write_value(cs, rbuffer->buf->size - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1976 r600_write_value(cs, /* RESOURCEi_WORD2 */
1980 r600_write_value(cs, /* RESOURCEi_WORD3 */
1985 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1986 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1987 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
1988 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1990 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1991 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
2013 struct radeon_winsys_cs *cs = rctx->cs;
2029 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
2031 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, va >> 8);
2033 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2034 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
2036 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
2037 r600_write_value(cs, (buffer_id_base + buffer_index) * 8);
2038 r600_write_value(cs, va); /* RESOURCEi_WORD0 */
2039 r600_write_value(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2040 r600_write_value(cs, /* RESOURCEi_WORD2 */
2044 r600_write_value(cs, /* RESOURCEi_WORD3 */
2049 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
2050 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
2051 r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
2052 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
2054 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2055 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
2080 struct radeon_winsys_cs *cs = rctx->cs;
2091 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
2092 r600_write_value(cs, (resource_id_base + resource_index) * 8);
2093 r600_write_array(cs, 8, rview->tex_resource_words);
2098 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2099 r600_write_value(cs, reloc);
2100 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2101 r600_write_value(cs, reloc);
2121 struct radeon_winsys_cs *cs = rctx->cs;
2129 r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
2130 r600_write_value(cs, (resource_id_base + i) * 3);
2131 r600_write_array(cs, 3, texinfo->samplers[i]->tex_sampler_words);
2134 r600_write_config_reg_seq(cs, border_index_reg, 5);
2135 r600_write_value(cs, i);
2136 r600_write_array(cs, 4, texinfo->samplers[i]->border_color);
2156 r600_write_context_reg(rctx->cs, R_028C3C_PA_SC_AA_MASK,
2163 struct radeon_winsys_cs *cs = rctx->cs;
2166 r600_write_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2167 r600_write_value(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2168 r600_write_value(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
