Lines Matching full:opcode
55 result is required to be in the w slot, the opcode above may be
361 unsigned opcode = TGSI_OPCODE_BRK;
363 ctx->inst_info = &cm_shader_tgsi_instruction[opcode];
365 ctx->inst_info = &eg_shader_tgsi_instruction[opcode];
367 ctx->inst_info = &r600_shader_tgsi_instruction[opcode];
412 unsigned opcode = TGSI_OPCODE_CONT;
415 &cm_shader_tgsi_instruction[opcode];
418 &eg_shader_tgsi_instruction[opcode];
421 &r600_shader_tgsi_instruction[opcode];
1173 unsigned opcode;
1394 opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
1400 ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
1402 ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
1404 ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
1716 R600_ERR("%s tgsi opcode unsupported\n",
3762 int opcode;
3765 const boolean src_requires_loading = inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ &&
3768 unsigned sampler_src_reg = inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ? 0 : 1;
3773 if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
3782 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
3835 } else if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
3901 inst->Instruction.Opcode != TGSI_OPCODE_TXQ &&
3902 inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) {
4018 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
4019 inst->Instruction.Opcode == TGSI_OPCODE_TXL) {
4054 opcode = ctx->inst_info->r600_opcode;
4061 switch (opcode) {
4063 opcode = SQ_TEX_INST_SAMPLE_C;
4066 opcode = SQ_TEX_INST_SAMPLE_C_L;
4069 opcode = SQ_TEX_INST_SAMPLE_C_LB;
4072 opcode = SQ_TEX_INST_SAMPLE_C_G;
4078 tex.inst = opcode;
4089 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ) {
4134 opcode != SQ_TEX_INST_SAMPLE_C_L &&
4135 opcode != SQ_TEX_INST_SAMPLE_C_LB) {
4141 if (opcode == SQ_TEX_INST_SAMPLE_C_L ||
4142 opcode == SQ_TEX_INST_SAMPLE_C_LB) {
4760 switch (inst->Instruction.Opcode) {
4792 Opcode) {
4877 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
4883 alu.inst = opcode;
