Lines Matching full:instruction
53 // Function to initiate all of the instruction level optimizations.
73 // Run a series of tests to see if we can optimize a CALL instruction.
76 bool optimizeBitExtract(Instruction *inst);
78 bool optimizeBitInsert(Instruction *inst);
79 bool setupBitInsert(Instruction *base,
80 Instruction *&src,
83 // Expand the bit field insert instruction on versions of OpenCL that
86 // Expand the bit field mask instruction on version of OpenCL that
105 bool correctMisalignedMemOp(Instruction *inst);
300 Instruction *inst = (*bbb);
330 // call instruction to a vector and process
390 AMDGPUPeepholeOpt::setupBitInsert(Instruction *base,
391 Instruction *&src,
402 if (base->getOpcode() == Instruction::Shl) {
404 } else if (base->getOpcode() == Instruction::And) {
409 dbgs() << "Failed setup with no Shl or And instruction on base opcode!\n";
414 src = dyn_cast<Instruction>(base->getOperand(0));
417 dbgs() << "Failed setup since the base operand is not an instruction!\n";
427 if (src->getOpcode() == Instruction::Shl && !shift) {
429 src = dyn_cast<Instruction>(src->getOperand(0));
430 } else if (src->getOpcode() == Instruction::And && !mask) {
443 AMDGPUPeepholeOpt::optimizeBitInsert(Instruction *inst)
451 if (inst->getOpcode() != Instruction::Or) {
458 // single ISA instruction.
467 // The HD4XXX hardware doesn't support the ubit_insert instruction.
494 Instruction *LHSSrc = NULL, *RHSSrc = NULL;
497 Instruction *LHS = dyn_cast<Instruction>(inst->getOperand(0));
498 Instruction *RHS = dyn_cast<Instruction>(inst->getOperand(1));
602 LHSSrc = BinaryOperator::Create(Instruction::LShr, LHSSrc, offset,
605 LHSSrc = BinaryOperator::Create(Instruction::LShr, LHSSrc, offset,
624 LHSSrc = BinaryOperator::Create(Instruction::LShr, LHSSrc, offset,
627 LHSSrc = BinaryOperator::Create(Instruction::LShr, LHSSrc, offset,
683 AMDGPUPeepholeOpt::optimizeBitExtract(Instruction *inst)
691 if (inst->getOpcode() != Instruction::And) {
733 // If the first operand is not a shift instruction, then we can return as it
739 if (ShiftInst->getOpcode() == Instruction::Shl) {
868 BinaryOperator::Create(Instruction::And, CI->getOperand(0),
871 BinaryOperator::Create(Instruction::Xor, CI->getOperand(0), negOneConst,
873 rhs = BinaryOperator::Create(Instruction::And, rhs, CI->getOperand(2),
875 lhs = BinaryOperator::Create(Instruction::Or, lhs, rhs, "bfi_or", CI);
910 BinaryOperator::Create(Instruction::And, CI->getOperand(0),
912 lhs = BinaryOperator::Create(Instruction::Shl, newShiftConst,
914 lhs = BinaryOperator::Create(Instruction::Sub, lhs,
917 BinaryOperator::Create(Instruction::And, CI->getOperand(1),
919 lhs = BinaryOperator::Create(Instruction::Shl, lhs, rhs, "bfm_shl", CI);
927 Instruction *inst = (*bbb);
943 AMDGPUPeepholeOpt::correctMisalignedMemOp(Instruction *inst)
1034 BinaryOperator::Create(Instruction::Mul, CI->getOperand(0),
1094 BinaryOperator::Create(Instruction::FDiv, CI->getOperand(0),
1147 // all uses of the load instruction with the samplerVal and
