Lines Matching refs:AMDGPU
30 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
31 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
32 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
33 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
62 case AMDGPU::CLAMP_R600:
65 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
69 .addReg(AMDGPU::PRED_SEL_OFF);
73 case AMDGPU::FABS_R600:
76 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
80 .addReg(AMDGPU::PRED_SEL_OFF);
85 case AMDGPU::FNEG_R600:
88 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV))
92 .addReg(AMDGPU::PRED_SEL_OFF);
97 case AMDGPU::R600_LOAD_CONST:
100 unsigned ConstantReg = AMDGPU::R600_CReg32RegClass.getRegister(RegIndex);
101 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::COPY))
107 case AMDGPU::MASK_WRITE:
117 case AMDGPU::RAT_WRITE_CACHELESS_eg:
121 &AMDGPU::R600_TReg32_XRegClass);
123 &AMDGPU::R600_TReg32RegClass);
124 unsigned EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
129 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::MOV_IMM_I32),
131 .addReg(AMDGPU::ALU_LITERAL_X)
132 .addReg(AMDGPU::PRED_SEL_OFF)
134 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::LSHR_eg), NewAddr)
137 .addReg(AMDGPU::PRED_SEL_OFF);
145 case AMDGPU::RESERVE_REG:
150 AMDGPU::R600_TReg32RegClass.getRegister(ReservedIndex);
155 case AMDGPU::TXD:
157 unsigned t0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
158 unsigned t1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
160 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), t0)
164 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), t1)
168 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G))
177 case AMDGPU::TXD_SHADOW:
179 unsigned t0 = MRI.createVirtualRegister(AMDGPU::R600_Reg128RegisterClass);
180 unsigned t1 = MRI.createVirtualRegister(AMDGPU::R600_Reg128RegisterClass);
182 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), t0)
186 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), t1)
190 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_C_G))
199 case AMDGPU::BRANCH:
200 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
204 case AMDGPU::BRANCH_COND_f32:
207 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X))
208 .addReg(AMDGPU::PREDICATE_BIT)
213 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
215 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
218 case AMDGPU::BRANCH_COND_i32:
221 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X))
222 .addReg(AMDGPU::PREDICATE_BIT)
227 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
229 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
262 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
283 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
284 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, Reg, VT);
307 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
308 AMDGPU::T1_X, VT);
310 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
311 AMDGPU::T1_Y, VT);
313 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
314 AMDGPU::T1_Z, VT);
316 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
317 AMDGPU::T0_X, VT);
319 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
320 AMDGPU::T0_Y, VT);
322 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
323 AMDGPU::T0_Z, VT);
