Lines Matching refs:ISD
29 setOperationAction(ISD::MUL, MVT::i64, Expand);
36 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
38 setOperationAction(ISD::FSUB, MVT::f32, Expand);
40 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
41 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
43 setOperationAction(ISD::ROTL, MVT::i32, Custom);
45 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
46 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
48 setOperationAction(ISD::SETCC, MVT::i32, Custom);
249 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
250 case ISD::ROTL: return LowerROTL(Op, DAG);
251 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
252 case ISD::SETCC: return LowerSETCC(Op, DAG);
253 case ISD::INTRINSIC_VOID: {
271 // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
274 case ISD::INTRINSIC_WO_CHAIN: {
325 // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
342 ISD::SELECT_CC,
382 DAG.getNode(ISD::SUB, DL, VT,
397 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
409 ISD::NodeType ConversionOp = ISD::DELETED_NODE;
412 ConversionOp = ISD::UINT_TO_FP;
414 ConversionOp = ISD::SINT_TO_FP;
417 ConversionOp = ISD::FP_TO_SINT;
431 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
448 case ISD::SETOEQ:
449 case ISD::SETUEQ:
450 case ISD::SETEQ:
453 case ISD::SETONE:
454 case ISD::SETUNE:
455 case ISD::SETNE:
463 return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False);
466 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
488 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, HWTrue, HWFalse, CC);
492 Cond = DAG.getNode(ISD::FP_TO_SINT, DL, MVT::i32,
493 DAG.getNode(ISD::FNEG, DL, VT, Cond));
496 return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False);
508 ISD::SELECT_CC,
516 ISD::AND,
