Lines Matching refs:MVT
29 setOperationAction(ISD::MUL, MVT::i64, Expand);
30 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
31 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
32 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
33 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
36 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
38 setOperationAction(ISD::FSUB, MVT::f32, Expand);
40 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
41 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
43 setOperationAction(ISD::ROTL, MVT::i32, Custom);
45 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
46 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
48 setOperationAction(ISD::SETCC, MVT::i32, Custom);
344 MVT::i32,
346 DAG.getConstant(-1, MVT::i32),
347 DAG.getConstant(0, MVT::i32),
352 MVT::Other, Chain,
369 DAG.getConstant(ByteOffset, MVT::i32), // PTR
383 DAG.getConstant(32, MVT::i32),
410 if (VT == MVT::f32 && CompareVT == MVT::i32) {
416 } else if (VT == MVT::i32 && CompareVT == MVT::f32) {
475 if (VT == MVT::f32) {
478 } else if (VT == MVT::i32) {
491 if (VT == MVT::f32) {
492 Cond = DAG.getNode(ISD::FP_TO_SINT, DL, MVT::i32,
506 assert(Op.getValueType() == MVT::i32);
510 MVT::i32,
512 DAG.getConstant(-1, MVT::i32),
513 DAG.getConstant(0, MVT::i32),
518 MVT::i32,
519 DAG.getConstant(1, MVT::i32),
