Lines Matching refs:AMDGPU
32 Reserved.set(AMDGPU::ZERO);
33 Reserved.set(AMDGPU::HALF);
34 Reserved.set(AMDGPU::ONE);
35 Reserved.set(AMDGPU::ONE_INT);
36 Reserved.set(AMDGPU::NEG_HALF);
37 Reserved.set(AMDGPU::NEG_ONE);
38 Reserved.set(AMDGPU::PV_X);
39 Reserved.set(AMDGPU::ALU_LITERAL_X);
40 Reserved.set(AMDGPU::PREDICATE_BIT);
41 Reserved.set(AMDGPU::PRED_SEL_OFF);
42 Reserved.set(AMDGPU::PRED_SEL_ZERO);
43 Reserved.set(AMDGPU::PRED_SEL_ONE);
45 for (TargetRegisterClass::iterator I = AMDGPU::R600_CReg32RegClass.begin(),
46 E = AMDGPU::R600_CReg32RegClass.end(); I != E; ++I) {
62 case AMDGPU::GPRF32RegClassID:
63 case AMDGPU::GPRI32RegClassID:
64 return &AMDGPU::R600_Reg32RegClass;
72 case AMDGPU::ZERO: return 248;
73 case AMDGPU::ONE:
74 case AMDGPU::NEG_ONE: return 249;
75 case AMDGPU::ONE_INT: return 250;
76 case AMDGPU::HALF:
77 case AMDGPU::NEG_HALF: return 252;
78 case AMDGPU::ALU_LITERAL_X: return 253;
79 case AMDGPU::PREDICATE_BIT:
80 case AMDGPU::PRED_SEL_OFF:
81 case AMDGPU::PRED_SEL_ZERO:
82 case AMDGPU::PRED_SEL_ONE:
91 case AMDGPU::ZERO:
92 case AMDGPU::ONE:
93 case AMDGPU::ONE_INT:
94 case AMDGPU::NEG_ONE:
95 case AMDGPU::HALF:
96 case AMDGPU::NEG_HALF:
97 case AMDGPU::ALU_LITERAL_X:
98 case AMDGPU::PREDICATE_BIT:
99 case AMDGPU::PRED_SEL_OFF:
100 case AMDGPU::PRED_SEL_ZERO:
101 case AMDGPU::PRED_SEL_ONE:
112 case MVT::i32: return &AMDGPU::R600_TReg32RegClass;
120 case 0: return AMDGPU::sel_x;
121 case 1: return AMDGPU::sel_y;
122 case 2: return AMDGPU::sel_z;
123 case 3: return AMDGPU::sel_w;
