Lines Matching full:instruction
5 "Instruction fetch misses from cache or normal cacheable memory"},
7 "Instruction fetch misses from TLB"},
25 "Instruction that writes to the Context ID Register architecturally executed"},
29 "Immediate branch instruction executed (taken or not)"},
62 "L1 instruction cache miss as a result of the hashing algorithm"},
74 "Any L1 instruction cache access, excluding CP15 cache accesses"},
84 "Number of operations executed (in instruction or mutli-cycle instruction)"},
86 "Cycles where no instruction available"},
92 "Number of cycles the processor waits on NEON instruction queue or NEON load queue"},
