Lines Matching full:cycles
12 0x01 cycles Counts the cycles of store buffer drains
31 0x01 reset Counts memory disambiguration reset cycles
34 0x08 watch_cycles Counts the cycles that the memory disambiguration watchdog is active
42 0x01 stalled_cycles Counts the number of cycles no Uops issued by the Register Allocation Table to the Reservation Station, i
72 0x01 cycles_div_busy Counts the number of cycles the divider is busy executing divide or square root operations
78 0x02 cycles_masked Number of cycles interrupt are masked
79 0x04 cycles_pending_and_masked Number of cycles interrupts are pending and masked
130 0x00 thread_p Counts the number of thread cycles while the thread is not in a halt state
153 # 0x02 load_buffers_full Counts cycles of L1 data cache load fill buffers full
178 0x01 read_data Counts weighted cycles of offcore demand data read requests
179 0x02 read_code Counts weighted cycles of offcore demand code read requests
180 0x04 rfo Counts weighted cycles of offcore demand RFO requests
181 0x08 read Counts weighted cycles of offcore read requests of any kind
184 0x02 l1d Counts the number of cycles that cacheline in the L1 data cache unit is locked
198 0x04 walk_cycles Counts ITLB miss page walk cycles
199 0x04 pmh_busy_cycles Counts PMH busy cycles
205 0x01 lcp Cycles Instruction Length Decoder stalls due to length changing prefixes: 66, 67 or REX
206 0x02 mru Instruction Length Decoder stall cycles due to Brand Prediction Unit (PBU) Most Recently Used (MRU) bypass
207 0x04 iq_full Stall cycles due to a full instruction queue
209 0x0F any Counts any cycles the Instruction Length Decoder is stalled
234 0x02 load Counts the cycles of stall due to lack of load buffer for load operation
235 0x04 rs_full This event counts the number of cycles when the number of instructions in the pipeline waiting for execution reaches the limit the processor can handle
236 0x08 store This event counts the number of cycles that a resource related stall will occur due to the number of store instructions reaching the limit of the pipeline, (i
237 0x10 rob_full Counts the cycles of stall due to reorder buffer full
238 0x20 fpcw Counts the number of cycles while execution was stalled due to writing the floating-point unit (FPU) control word
240 0x80 other Counts the number of cycles while execution was stalled due to other resource issues
260 0x01 data Counts weighted cycles of snoopq requests for data
261 0x02 invalidate Counts weighted cycles of snoopq invalidate requests
262 0x04 code Counts weighted cycles of snoopq requests for code
278 0x01 cycles Counts the cycles machine clear is asserted
315 0x01 flags Counts the number of cycles during which execution stalled due to several reasons, one of which is a partial flag register stall
316 0x02 registers This event counts the number of cycles instruction execution latency became longer than the defined latency because the instruction used a register that was partially written by previous instruction
317 0x04 rob_read_port Counts the number of cycles when ROB read port stalls occurred, which did not allow new micro-ops to enter the out-of-order pipeline
318 0x08 scoreboard Counts the cycles where we stall due to microarchitecturally required serialization
319 0x0F any Counts all Register Allocation Table stall cycles due to: Cycles when ROB read port stalls occurred, which did not allow new micro-ops to enter the execution pipe
