Lines Matching full:where
27 0x20 pde_miss Number of DTLB cache load misses where the low part of the linear to physical address translation was missed
28 0x40 pdp_miss Number of DTLB cache load misses where the high part of the linear to physical address translation was missed
45 0x02 other_core_l2_hitm Counts number of memory load instructions retired where the memory reference hit modified data in a sibling core residing on the same socket
46 0x08 remote_cache_local_home_hit Counts number of memory load instructions retired where the memory reference missed the L1, L2 and LLC caches and HIT in a remote socket's cache
47 0x10 remote_dram Counts number of memory load instructions retired where the memory reference missed the L1, L2 and LLC caches and was remotely homed
48 0x20 local_dram Counts number of memory load instructions retired where the memory reference missed the L1, L2 and LLC caches and required a local socket memory reference
96 0x01 i_state Counts number of L2 data demand loads where the cache line to be loaded is in the I (invalid) state, i
97 0x02 s_state Counts number of L2 data demand loads where the cache line to be loaded is in the S (shared) state
98 0x04 e_state Counts number of L2 data demand loads where the cache line to be loaded is in the E (exclusive) state
99 0x08 m_state Counts number of L2 data demand loads where the cache line to be loaded is in the M (modified) state
101 0x10 i_state Counts number of L2 prefetch data loads where the cache line to be loaded is in the I (invalid) state, i
102 0x20 s_state Counts number of L2 prefetch data loads where the cache line to be loaded is in the S (shared) state
103 0x40 e_state Counts number of L2 prefetch data loads where the cache line to be loaded is in the E (exclusive) state
104 0x80 m_state Counts number of L2 prefetch data loads where the cache line to be loaded is in the M (modified) state
108 0x01 i_state Counts number of L2 demand store RFO requests where the cache line to be loaded is in the I (invalid) state, i
109 0x02 s_state Counts number of L2 store RFO requests where the cache line to be loaded is in the S (shared) state
110 0x04 e_state Counts number of L2 store RFO requests where the cache line to be loaded is in the E (exclusive) state
111 0x08 m_state Counts number of L2 store RFO requests where the cache line to be loaded is in the M (modified) state
112 0x0E hit Counts number of L2 store RFO requests where the cache line to be loaded is in either the S, E or M states
114 0x10 i_state Counts number of L2 demand lock RFO requests where the cache line to be loaded is in the I (invalid) state, i
115 0x20 s_state Counts number of L2 lock RFO requests where the cache line to be loaded is in the S (shared) state
116 0x40 e_state Counts number of L2 demand lock RFO requests where the cache line to be loaded is in the E (exclusive) state
117 0x80 m_state Counts number of L2 demand lock RFO requests where the cache line to be loaded is in the M (modified) state
118 0xE0 hit Counts number of L2 demand lock RFO requests where the cache line to be loaded is in either the S, E, or M state
121 0x01 i_state Counts number of L1 writebacks to the L2 where the cache line to be written is in the I (invalid) state, i
122 0x02 s_state Counts number of L1 writebacks to the L2 where the cache line to be written is in the S state
123 0x04 e_state Counts number of L1 writebacks to the L2 where the cache line to be written is in the E (exclusive) state
124 0x08 m_state Counts number of L1 writebacks to the L2 where the cache line to be written is in the M (modified) state
133 0x01 i_state Counts L1 data cache read requests where the cache line to be loaded is in the I (invalid) state, i
134 0x02 s_state Counts L1 data cache read requests where the cache line to be loaded is in the S (shared) state
135 0x04 e_state Counts L1 data cache read requests where the cache line to be loaded is in the E (exclusive) state
136 0x08 m_state Counts L1 data cache read requests where the cache line to be loaded is in the M (modified) state
139 0x01 i_state Counts L1 data cache store RFO requests where the cache line to be loaded is in the I state
140 0x02 s_state Counts L1 data cache store RFO requests where the cache line to be loaded is in the S (shared) state
141 0x04 e_state Counts L1 data cache store RFO requests where the cache line to be loaded is in the E (exclusive) state
142 0x08 m_state Counts L1 data cache store RFO requests where cache line to be loaded is in the M (modified) state
158 0x20 pde_miss Number of DTLB cache misses where the low part of the linear to physical address translation was missed
159 0x40 pdp_miss Number of DTLB misses where the high part of the linear to physical address translation was missed
201 0x20 pde_miss Number of ITLB misses where the low part of the linear to physical address translation was missed
202 0x40 pdp_miss Number of ITLB misses where the high part of the linear to physical address translation was missed
255 0x10 port4_core Counts number of Uops executed that where issued on port 4
256 0x20 port5 Counts number of Uops executed that where issued on port 5
257 0x40 port015 Counts number of Uops executed that where issued on port 0, 1, or 5
258 0x80 port234 Counts number of Uops executed that where issued on port 2, 3, or 4
313 0x08 esp_sync Counts number of stack pointer (ESP) sync operations where an ESP instruction is corrected by adding the ESP offset register to the current value of the ESP register
318 0x08 scoreboard Counts the cycles where we stall due to microarchitecturally required serialization
