Lines Matching full:cycles
2 {0x0, CTR(0) | CTR(1), 0, "CYCLES",
3 "0-0 Cycles"},
37 "18-0 Stall cycles, including ALU and IFU"},
49 "24-0 Cache fixup cycles (specific to the 34K family microarchitecture)"},
51 "25-0 IFU stall cycles"},
71 "36-0 Cache coherence intervention processing stall cycles"},
73 "37-0 Stall cycles due to an instruction cache miss"},
75 "39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipeline"},
77 "40-0 Uncached stall cycles"},
79 "41-0 MDU stall cycles"},
81 "42-0 CP2 stall cycles"},
83 "43-0 ISPRAM stall cycles"},
87 "45-0 Load to use stall cycles"},
89 "46-0 Stall cycles due to return data from MFC0, RDHWR, and MFTR instructions"},
91 "47-0 Low power stall cycles (operations) as requested by the policy manager"},
161 "23-1 Cycles while one and only one TC is eligible for scheduling"},
165 "25-1 ALU stall cycles"},
181 "36-1 Cache coherence intervention processing stall cycles due to an earlier miss"},
183 "37-1 Stall cycles due to a data cache miss"},
185 "38-1 FSB (fill/store buffer) index conflict stall cycles"},
187 "39-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline"},
189 "40-1 ITC stall cycles"},
191 "41-1 FPU stall cycles"},
193 "42-1 CorExtend stall cycles"},
195 "43-1 DSPRAM stall cycles"},
197 "45-1 ALU to AGEN stall cycles"},
199 "46-1 Branch mispredict stall cycles"},
201 "48-1 Cycles while at least one IFU fill buffer is allocated"},
207 "51-1 FSB full pipeline stall cycles"},
211 "53-1 LDQ full pipeline stall cycles"},
215 "55-1 WBB full pipeline stall cycles"},
