Lines Matching full:default
9 name:zero type:mandatory default:0x0
11 name:PPU_0_cycles type:bitmask default:0x013
14 0x002 Positive polarity [default ]
16 name:PPU_0_edges type:bitmask default:0x012
19 0x002 Positive polarity [default ]
21 name:PPU_2_cycles type:bitmask default:0x043
24 0x002 Positive polarity [default ]
26 name:PPU_2_edges type:bitmask default:0x042
29 0x002 Positive polarity [default ]
31 name:PPU_01_cycles type:bitmask default:0x023
34 0x002 Positive polarity [default ]
36 0x020 PPU Bus Word 1 [default ]
37 name:PPU_01_edges type:bitmask default:0x022
40 0x002 Positive polarity [default ]
42 0x020 PPU Bus Word 1 [default ]
43 name:PPU_01_cycles_or_edges type:bitmask default:0x023
45 0x001 Count cycles [default ]
47 0x002 Positive polarity [default ]
49 0x020 PPU Bus Word 1 [default ]
50 name:PPU_02_cycles type:bitmask default:0x013
53 0x002 Positive polarity [default ]
54 0x010 PPU Bus Word 0 [default ]
56 name:PPU_02_edges type:bitmask default:0x012
59 0x002 Positive polarity [default ]
60 0x010 PPU Bus Word 0 [default ]
62 name:PPU_02_cycles_or_edges type:bitmask default:0x013
64 0x001 Count cycles [default ]
66 0x002 Positive polarity [default ]
67 0x010 PPU Bus Word 0 [default ]
69 name:PPU_0123_cycles type:bitmask default:0x033
72 0x002 Positive polarity [default ]
73 0x030 PPU Bus Word 0/1 [default ]
75 name:SPU_02_cycles type:bitmask default:0x0113
78 0x0002 Positive polarity [default ]
79 0x0110 SPU Bus Word 0 [default ]
81 0x0000 SPU 0 [default ]
89 name:SPU_02_cycles_or_edges type:bitmask default:0x0113
91 0x0001 Count cycles [default ]
93 0x0002 Positive polarity [default ]
94 0x0110 SPU Bus Word 0 [default ]
96 0x0000 SPU 0 [default ]
104 name:SPU_Trigger_cycles_or_edges type:bitmask default:0x0107
106 0x0001 Count cycles [default ]
108 0x0002 Positive polarity [default ]
109 0x0104 SPU Trigger 0 [default ]
113 0x0000 SPU 0 [default ]
121 name:SPU_Event_cycles_or_edges type:bitmask default:0x0147
123 0x0001 Count cycles [default ]
125 0x0002 Positive polarity [default ]
126 0x0144 SPU Event 0 [default ]
130 0x0000 SPU 0 [default ]
