Lines Matching refs:val8
993 #define SET_AL(val8) AX = ((AX & 0xff00) | (val8))
994 #define SET_BL(val8) BX = ((BX & 0xff00) | (val8))
995 #define SET_CL(val8) CX = ((CX & 0xff00) | (val8))
996 #define SET_DL(val8) DX = ((DX & 0xff00) | (val8))
997 #define SET_AH(val8) AX = ((AX & 0x00ff) | ((val8) << 8))
998 #define SET_BH(val8) BX = ((BX & 0x00ff) | ((val8) << 8))
999 #define SET_CH(val8) CX = ((CX & 0x00ff) | ((val8) << 8))
1000 #define SET_DH(val8) DX = ((DX & 0x00ff) | ((val8) << 8))
6880 Bit8u val8;
6883 val8 = inb(0x03f2);
6884 outb(0x03f2, val8 & ~0x04);
6885 outb(0x03f2, val8 | 0x04);
6889 val8 = inb(0x3f4);
6890 } while ( (val8 & 0xc0) != 0x80 );
6896 Bit8u val8, dor, prev_reset;
6899 val8 = read_byte(0x0040, 0x003e);
6900 val8 &= 0x7f;
6901 write_byte(0x0040, 0x003e, val8);
6918 val8 = inb(0x3f4);
6919 } while ( (val8 & 0xc0) != 0x80 );
6928 val8 = read_byte(0x0040, 0x003e);
6929 } while ( (val8 & 0x80) == 0 );
6930 val8 &= 0x7f;
6934 write_byte(0x0040, 0x003e, val8);
6942 Bit8u val8;
6945 val8 = read_byte(0x0040, 0x003e); // diskette recal status
6947 val8 >>= 1;
6948 val8 &= 0x01;
6949 if (val8 == 0)
6956 val8 = read_byte(0x0040, media_state_offset);
6957 val8 = (val8 >> 4) & 0x01;
6958 if (val8 == 0)
7085 Bit8u val8;
7101 val8 = (read_byte(0x0040, 0x003e) & 0x80);
7102 } while ( val8 == 0 );
7104 val8 = 0; // separate asm from while() loop
7111 val8 = read_byte(0x0040, 0x003e);
7112 val8 &= 0x7f;
7114 val8 |= 0x02; // Drive 1 calibrated
7117 val8 |= 0x01; // Drive 0 calibrated
7120 write_byte(0x0040, 0x003e, val8);
7152 Bit8u page, mode_register, val8, dor;
7191 val8 = read_byte(0x0000, 0x0441);
7192 SET_AH(val8);
7193 if (val8) {
7318 val8 = read_byte(0x0040, 0x0040);
7319 if (val8 == 0) {
7327 val8 = (read_byte(0x0040, 0x003e) & 0x80);
7328 } while ( val8 == 0 );
7330 val8 = 0; // separate asm from while() loop
7337 val8 = read_byte(0x0040, 0x003e);
7338 val8 &= 0x7f;
7339 write_byte(0x0040, 0x003e, val8);
7342 val8 = inb(0x3f4);
7343 if ( (val8 & 0xc0) != 0xc0 )
7452 val8 = read_byte(0x0040, 0x0040);
7453 if (val8 == 0) {
7461 val8 = (read_byte(0x0040, 0x003e) & 0x80);
7462 } while ( val8 == 0 );
7464 val8 = 0; // separate asm from while() loop
7471 val8 = read_byte(0x0040, 0x003e);
7472 val8 &= 0x7f;
7473 write_byte(0x0040, 0x003e, val8);
7476 val8 = inb(0x3f4);
7477 if ( (val8 & 0xc0) != 0xc0 )
7615 val8 = read_byte(0x0040, 0x0040);
7616 if (val8 == 0) {
7623 val8 = (read_byte(0x0040, 0x003e) & 0x80);
7624 } while ( val8 == 0 );
7626 val8 = 0; // separate asm from while() loop
7632 val8 = read_byte(0x0040, 0x003e);
7633 val8 &= 0x7f;
7634 write_byte(0x0040, 0x003e, val8);
7636 val8 = inb(0x3f4);
7637 if ( (val8 & 0xc0) != 0xc0 )
7847 Bit8u val8;
7853 val8 = read_byte(0x0000, 0x0441);
7854 SET_AH(val8);
7855 if (val8) {
7890 Bit8u val8, DOR, ctrl_info;
7914 val8 = inb(0x03f4) & 0x80; // Main Status Register
7915 if (val8 != 0x80)
7937 Bit8u val8;
7948 val8 = inb(addr+2);
7949 outb(addr+2, val8 | 0x01); // send strobe
7953 outb(addr+2, val8 & ~0x01);
7959 val8 = inb(addr+2);
7960 outb(addr+2, val8 & ~0x04); // send init
7964 outb(addr+2, val8 | 0x04);
7966 val8 = inb(addr+1);
7967 regs.u.r8.ah = (val8 ^ 0x48);
8162 Bit8u val8;
8235 val8 = (inb_cmos(0x0b) & 0x60) | 0x02 | (regs.u.r8.dl & 0x01);
8237 outb_cmos(0x0b, val8);
8239 regs.u.r8.al = val8; // val last written to Reg B
8277 val8 = inb_cmos(0x0b) & 0x7f; // clear halt-clock bit
8278 outb_cmos(0x0b, val8);
8280 regs.u.r8.al = val8; // AL = val last written to Reg B
8295 val8 = inb_cmos(0x0b); // Get Status Reg B
8297 if (val8 & 0x20) {
8311 outb_cmos(0x0b, (val8 & 0x7f) | 0x20);
8326 val8 = inb_cmos(0x0b); // Get Status Reg B
8328 outb_cmos(0x0b, val8 & 0x57); // disable alarm bit
8330 regs.u.r8.al = val8; // val last written to Reg B