Lines Matching defs:rd
1322 int rd;
1326 rd = (insn >> 16) & 0xf;
1327 tmp = load_reg(s, rd);
1338 store_reg(s, rd, tmp);
1348 store_reg(s, rd, tmp);
1356 int rd = (insn >> 0) & 0xf;
1360 if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3) {
1363 tmp = iwmmxt_load_creg(rd);
1367 iwmmxt_load_reg(cpu_V0, rd);
1380 int rd, wrd;
1484 rd = (insn >> 12) & 0xf;
1495 tmp2 = load_reg(s, rd);
1505 tmp = load_reg(s, rd);
1526 rd = (insn >> 12) & 0xf;
1529 store_reg(s, rd, tmp);
1717 rd = (insn >> 12) & 0xf;
1719 tmp = load_reg(s, rd);
1746 rd = (insn >> 12) & 0xf;
1748 if (rd == 15 || ((insn >> 22) & 3) == 3)
1776 store_reg(s, rd, tmp);
1800 rd = (insn >> 12) & 0xf;
1802 tmp = load_reg(s, rd);
1895 rd = (insn >> 12) & 0xf;
1912 store_reg(s, rd, tmp);
2455 uint32_t rd = (insn >> 12) & 0xf;
2466 store_reg(s, rd, tmp);
2471 tmp = load_reg(s, rd);
2500 static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, uint32_t rd)
2527 store_reg(s, rd, tmp);
2530 tmp = load_reg(s, rd);
2553 uint32_t rd;
2607 rd = (insn >> 12) & 0xf;
2609 if (cp15_tls_load_store(env, s, insn, rd))
2617 if (rd != 15)
2618 store_reg(s, rd, tmp);
2622 tmp = load_reg(s, rd);
2727 uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
2750 rd = (insn >> 12) & 0xf;
2803 store_reg(s, rd, tmp);
2806 tmp = load_reg(s, rd);
2873 if (rd == 15) {
2895 if (rd == 15) {
2900 store_reg(s, rd, tmp);
2904 tmp = load_reg(s, rd);
2956 rd = VFP_SREG_D(insn);
2958 VFP_DREG_D(rd, insn);
2973 VFP_DREG_D(rd, insn);
2975 rd = VFP_SREG_D(insn);
2999 if ((rd & bank_mask) == 0) {
3029 gen_mov_F0_vreg(dp, rd);
3035 gen_mov_F0_vreg(dp, rd);
3047 gen_mov_F0_vreg(dp, rd);
3066 gen_mov_F0_vreg(dp, rd);
3072 gen_mov_F0_vreg(dp, rd);
3081 gen_mov_F0_vreg(dp, rd);
3088 gen_mov_F0_vreg(dp, rd);
3165 gen_mov_F0_vreg(0, rd);
3178 gen_mov_F0_vreg(0, rd);
3277 gen_mov_vreg_F0(0, rd);
3280 gen_mov_vreg_F0(!dp, rd);
3282 gen_mov_vreg_F0(dp, rd);
3291 rd = ((rd + delta_d) & (bank_mask - 1))
3292 | (rd & bank_mask);
3293 gen_mov_vreg_F0(dp, rd);
3299 rd = ((rd + delta_d) & (bank_mask - 1))
3300 | (rd & bank_mask);
3326 rd = (insn >> 12) & 0xf;
3338 store_reg(s, rd, tmp);
3345 store_reg(s, rd, tmp);
3353 tmp = load_reg(s, rd);
3360 tmp = load_reg(s, rd);
3372 VFP_DREG_D(rd, insn);
3374 rd = VFP_SREG_D(insn);
3389 gen_mov_vreg_F0(dp, rd);
3391 gen_mov_F0_vreg(dp, rd);
3414 gen_mov_vreg_F0(dp, rd + i);
3417 gen_mov_F0_vreg(dp, rd + i);
3687 static int gen_neon_unzip(int rd, int rm, int size, int q)
3693 tmp = tcg_const_i32(rd);
3726 static int gen_neon_zip(int rd, int rm, int size, int q)
3732 tmp = tcg_const_i32(rd);
3767 TCGv rd, tmp;
3769 rd = tcg_temp_new_i32();
3772 tcg_gen_shli_i32(rd, t0, 8);
3773 tcg_gen_andi_i32(rd, rd, 0xff00ff00);
3775 tcg_gen_or_i32(rd, rd, tmp);
3781 tcg_gen_mov_i32(t0, rd);
3784 tcg_temp_free_i32(rd);
3789 TCGv rd, tmp;
3791 rd = tcg_temp_new_i32();
3794 tcg_gen_shli_i32(rd, t0, 16);
3796 tcg_gen_or_i32(rd, rd, tmp);
3800 tcg_gen_mov_i32(t0, rd);
3803 tcg_temp_free_i32(rd);
3829 int rd, rn, rm;
3846 VFP_DREG_D(rd, insn);
3910 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 0));
3911 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 1));
3913 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd + 1, 0));
3914 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd + 1, 1));
3922 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 0));
3923 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 1));
3926 rd += stride;
3978 if ((rd + stride * (nregs - 1)) > 31) {
4003 tmp2 = neon_load_reg(rd, pass);
4007 neon_store_reg(rd, pass, tmp);
4009 tmp = neon_load_reg(rd, pass);
4024 rd += stride;
4420 int rd, rn, rm;
4435 VFP_DREG_D(rd, insn);
4449 if (q && ((rd | rn | rm) & 1)) {
4510 neon_store_reg64(cpu_V0, rd + pass);
4618 tmp3 = neon_load_reg(rd, pass);
4623 tmp3 = neon_load_reg(rd, pass);
4628 tmp3 = neon_load_reg(rd, pass);
4670 tmp2 = neon_load_reg(rd, pass);
4710 tmp2 = neon_load_reg(rd, pass);
4780 tmp2 = neon_load_reg(rd, pass);
4824 if (pairwise && rd == rm) {
4827 neon_store_reg(rd, pass, tmp);
4831 if (pairwise && rd == rm) {
4834 neon_store_reg(rd, pass, tmp);
4859 if (q && ((rd | rm) & 1)) {
4930 neon_load_reg64(cpu_V1, rd + pass);
4934 neon_load_reg64(cpu_V1, rd + pass);
4948 neon_store_reg64(cpu_V0, rd + pass);
4994 tmp2 = neon_load_reg(rd, pass);
5028 tmp2 = neon_load_reg(rd, pass);
5034 neon_store_reg(rd, pass, tmp);
5072 neon_store_reg(rd, pass, tmp);
5106 neon_store_reg(rd, pass, tmp);
5112 if (q || (rd & 1)) {
5151 neon_store_reg64(cpu_V0, rd + pass);
5155 if (!(insn & (1 << 21)) || (q && ((rd | rm) & 1))) {
5175 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, pass));
5182 if (q && (rd & 1)) {
5237 tmp = neon_load_reg(rd, pass);
5261 neon_store_reg(rd, pass, tmp);
5310 (!src2_wide && (rd & 1))) {
5317 if (rd == rm && !src2_wide) {
5320 } else if (rd == rn && !src1_wide) {
5330 if (pass == 1 && rd == rn) {
5343 if (pass == 1 && rd == rm) {
5399 neon_store_reg64(cpu_V0, rd + pass);
5402 neon_load_reg64(cpu_V1, rd + pass);
5420 neon_store_reg64(cpu_V0, rd + pass);
5457 neon_store_reg(rd, 0, tmp3);
5458 neon_store_reg(rd, 1, tmp);
5462 neon_store_reg64(cpu_V0, rd + pass);
5486 if (u && ((rd | rn) & 1)) {
5519 tmp2 = neon_load_reg(rd, pass);
5538 neon_store_reg(rd, pass, tmp);
5551 if (rd & 1) {
5570 neon_load_reg64(cpu_V1, rd + pass);
5595 neon_store_reg64(cpu_V0, rd + pass);
5612 if (q && ((rd | rn | rm) & 1)) {
5656 neon_store_reg64(cpu_V0, rd);
5658 neon_store_reg64(cpu_V1, rd + 1);
5669 q && ((rm | rd) & 1)) {
5683 neon_store_reg(rd, pass * 2 + 1, tmp);
5685 neon_store_reg(rd, pass * 2, tmp2);
5692 neon_store_reg(rd, pass * 2, tmp2);
5711 neon_load_reg64(cpu_V1, rd + pass);
5714 neon_store_reg64(cpu_V0, rd + pass);
5722 tmp2 = neon_load_reg(rd, n + 1);
5724 neon_store_reg(rd, n + 1, tmp);
5731 if (gen_neon_unzip(rd, rm, size, q)) {
5736 if (gen_neon_zip(rd, rm, size, q)) {
5754 neon_store_reg(rd, 0, tmp2);
5755 neon_store_reg(rd, 1, tmp);
5760 if (q || (rd & 1)) {
5770 neon_store_reg64(cpu_V0, rd + pass);
5789 neon_store_reg(rd, 0, tmp2);
5794 neon_store_reg(rd, 1, tmp2);
5799 q || (rd & 1)) {
5807 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 0));
5810 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 1));
5814 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 2));
5817 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 3));
5961 tmp2 = neon_load_reg(rd, pass);
5965 tmp2 = neon_load_reg(rd, pass);
6005 neon_reg_offset(rd, pass));
6007 neon_store_reg(rd, pass, tmp);
6023 tmp = neon_load_reg(rd, 0);
6034 tmp = neon_load_reg(rd, 1);
6043 neon_store_reg(rd, 0, tmp2);
6044 neon_store_reg(rd, 1, tmp3);
6048 if ((insn & (7 << 16)) == 0 || (q && (rd & 1))) {
6067 neon_store_reg(rd, pass, tmp2);
6270 /* Load 64-bit value rd:rn. */
6337 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
6342 size | (rd << 4) | (rt << 8) | (rt2 << 12));
6346 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
6355 {Rd} = 0;
6357 {Rd} = 1;
6406 tcg_gen_movi_i32(cpu_R[rd], 0);
6409 tcg_gen_movi_i32(cpu_R[rd], 1);
6417 unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
6668 rd = (insn >> 12) & 0xf;
6676 tmp = load_reg(s, rd);
6680 store_reg(s, rd, tmp);
6713 rd = (insn >> 12) & 0xf;
6722 store_reg(s, rd, tmp);
6734 rd = (insn >> 12) & 0xf;
6737 store_reg(s, rd, tmp);
6766 rd = (insn >> 12) & 0xf;
6777 store_reg(s, rd, tmp);
6801 rd = (insn >> 16) & 0xf;
6820 store_reg(s, rd, tmp);
6831 gen_addq(s, tmp64, rn, rd);
6832 gen_storeq_reg(s, rn, rd, tmp64);
6840 store_reg(s, rd, tmp);
6889 rd = (insn >> 12) & 0xf;
6896 store_reg_bx(env, s, rd, tmp);
6903 store_reg_bx(env, s, rd, tmp);
6906 if (set_cc && rd == 15) {
6919 store_reg_bx(env, s, rd, tmp);
6928 store_reg_bx(env, s, rd, tmp);
6936 store_reg_bx(env, s, rd, tmp);
6944 store_reg_bx(env, s, rd, tmp);
6952 store_reg_bx(env, s, rd, tmp);
6960 store_reg_bx(env, s, rd, tmp);
6993 store_reg_bx(env, s, rd, tmp);
6996 if (logic_cc && rd == 15) {
7006 store_reg_bx(env, s, rd, tmp2);
7014 store_reg_bx(env, s, rd, tmp);
7022 store_reg_bx(env, s, rd, tmp2);
7038 rd = (insn >> 16) & 0xf;
7064 store_reg(s, rd, tmp);
7073 gen_addq_lo(s, tmp64, rd);
7074 gen_storeq_reg(s, rn, rd, tmp64);
7088 gen_addq(s, tmp64, rn, rd);
7093 gen_storeq_reg(s, rn, rd, tmp64);
7101 rd = (insn >> 12) & 0xf;
7114 gen_load_exclusive(s, rd, 15, addr, 2);
7117 gen_load_exclusive(s, rd, rd + 1, addr, 3);
7120 gen_load_exclusive(s, rd, 15, addr, 0);
7123 gen_load_exclusive(s, rd, 15, addr, 1);
7132 gen_store_exclusive(s, rd, rm, 15, addr, 2);
7135 gen_store_exclusive(s, rd, rm, rm + 1, addr, 3);
7138 gen_store_exclusive(s, rd, rm, 15, addr, 0);
7141 gen_store_exclusive(s, rd, rm, 15, addr, 1);
7165 store_reg(s, rd, tmp2);
7173 rd = (insn >> 12) & 0xf;
7198 tmp = load_reg(s, rd);
7201 tmp = load_reg(s, rd + 1);
7207 store_reg(s, rd, tmp);
7210 rd++;
7216 tmp = load_reg(s, rd);
7236 store_reg(s, rd, tmp);
7250 rd = (insn >> 12) & 0xf;
7262 store_reg(s, rd, tmp);
7286 store_reg(s, rd, tmp);
7305 store_reg(s, rd, tmp);
7316 store_reg(s, rd, tmp);
7326 store_reg(s, rd, tmp);
7353 store_reg(s, rd, tmp);
7370 store_reg(s, rd, tmp);
7383 if (rd != 15) {
7384 tmp = load_reg(s, rd);
7419 gen_addq(s, tmp64, rd, rn);
7420 gen_storeq_reg(s, rd, rn, tmp64);
7424 if (rd != 15)
7426 tmp2 = load_reg(s, rd);
7443 if (rd != 15) {
7444 tmp2 = load_reg(s, rd);
7463 tmp2 = load_reg(s, rd);
7467 store_reg(s, rd, tmp);
7484 store_reg(s, rd, tmp);
7505 rd = (insn >> 12) & 0xf;
7519 tmp = load_reg(s, rd);
7535 store_reg_from_load(env, s, rd, tmp);
7782 uint32_t rd, rn, rm, rs;
7846 rd = (insn >> 8) & 0xf;
7876 store_reg(s, rd, tmp);
7882 tmp = load_reg(s, rd);
7902 gen_store_exclusive(s, rd, rs, 15, addr, 2);
7938 gen_load_exclusive(s, rs, rd, addr, op);
7940 gen_store_exclusive(s, rm, rs, rd, addr, op);
8080 store_reg(s, rd, tmp);
8099 if (rd != 15) {
8100 store_reg(s, rd, tmp);
8121 store_reg_bx(env, s, rd, tmp);
8149 store_reg(s, rd, tmp);
8160 store_reg(s, rd, tmp);
8205 store_reg(s, rd, tmp);
8301 store_reg(s, rd, tmp);
8316 store_reg(s, rd, tmp);
8332 gen_addq(s, tmp64, rs, rd);
8333 gen_storeq_reg(s, rs, rd, tmp64);
8355 gen_addq_lo(s, tmp64, rd);
8358 gen_addq(s, tmp64, rs, rd);
8360 gen_storeq_reg(s, rs, rd, tmp64);
8496 if (rn != 14 || rd != 15) {
8512 store_reg(s, rd, tmp);
8519 store_reg(s, rd, tmp);
8581 tmp2 = load_reg(s, rd);
8612 store_reg(s, rd, tmp);
8621 tmp = load_reg(s, rd);
8647 store_reg(s, rd, tmp);
8690 rd = (insn >> 8) & 0xf;
8691 if (rd != 15) {
8692 store_reg(s, rd, tmp);
8852 uint32_t val, insn, op, rm, rn, rd, shift, cond;
8879 rd = insn & 7;
8906 store_reg(s, rd, tmp);
8915 store_reg(s, rd, tmp);
8921 rd = (insn >> 8) & 0x7;
8927 store_reg(s, rd, tmp);
8929 tmp = load_reg(s, rd);
8944 store_reg(s, rd, tmp);
8952 store_reg(s, rd, tmp);
8959 rd = (insn >> 8) & 7;
8967 store_reg(s, rd, tmp);
8972 rd = (insn & 7) | ((insn >> 4) & 8);
8977 tmp = load_reg(s, rd);
8981 store_reg(s, rd, tmp);
8984 tmp = load_reg(s, rd);
8992 store_reg(s, rd, tmp);
9011 rd = insn & 7;
9017 rm = rd;
9018 rd = val;
9028 tmp = load_reg(s, rd);
9093 rd = 16;
9103 rd = 16;
9107 rd = 16;
9129 rm = rd;
9132 if (rd != 16) {
9138 store_reg(s, rd, tmp);
9149 rd = insn & 7;
9159 tmp = load_reg(s, rd);
9188 store_reg(s, rd, tmp);
9194 rd = insn & 7;
9203 store_reg(s, rd, tmp);
9206 tmp = load_reg(s, rd);
9214 rd = insn & 7;
9223 store_reg(s, rd, tmp);
9226 tmp = load_reg(s, rd);
9234 rd = insn & 7;
9243 store_reg(s, rd, tmp);
9246 tmp = load_reg(s, rd);
9254 rd = (insn >> 8) & 7;
9262 store_reg(s, rd, tmp);
9265 tmp = load_reg(s, rd);
9273 rd = (insn >> 8) & 7;
9284 store_reg(s, rd, tmp);
9303 rd = insn & 7;
9312 store_reg(s, rd, tmp);
9405 rd = insn & 0x7;
9413 store_reg(s, rd, tmp);
