Lines Matching refs:cpu_env
64 static TCGv_ptr cpu_env;
279 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_B_OFFSET);
281 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);
285 tcg_gen_st16_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
289 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
292 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
296 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, regs[reg]));
301 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
321 tcg_gen_st16_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
325 tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
328 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
332 tcg_gen_st_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]));
337 tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
350 tcg_gen_ld8u_tl(t0, cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);
355 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, regs[reg]));
367 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
402 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, eip));
409 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
411 tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
414 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
419 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
423 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
425 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
435 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
437 tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
440 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
445 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
449 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
451 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
464 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
475 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base) + REG_L_OFFSET);
480 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
490 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base));
495 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
501 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]));
506 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
605 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, eip));
666 tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUState, df));
706 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ECX]));
713 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ECX]));
2372 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
2379 tcg_gen_st32_tl(cpu_T[0], cpu_env,
2382 tcg_gen_st_tl(cpu_T[0], cpu_env,
2747 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
2753 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
2761 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2764 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2770 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2773 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2779 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2780 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2781 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8);
2782 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8);
2787 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2788 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2793 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset);
2794 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset);
2800 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
3174 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
3179 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3189 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3196 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3208 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3210 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3233 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3235 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3236 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3237 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3249 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3250 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3328 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3334 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3342 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3348 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3392 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3437 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3439 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1)));
3443 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0)));
3445 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1)));
3458 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3459 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset);
3464 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3472 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3490 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3491 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3507 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3530 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3531 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3558 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3567 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3583 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3587 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3600 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3605 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3641 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm]));
3645 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx));
3687 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset +
3693 tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset +
3716 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3717 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3776 tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3785 tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3795 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
3806 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3820 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3834 tcg_gen_st8_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State,
3839 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
3847 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
3852 cpu_env, offsetof(CPUX86State,
3856 cpu_env, offsetof(CPUX86State,
3860 cpu_env, offsetof(CPUX86State,
3864 cpu_env, offsetof(CPUX86State,
3875 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
3885 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3926 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3927 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3955 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3986 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3987 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3993 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3994 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4003 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4004 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4023 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4024 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4028 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4029 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4839 tcg_gen_ld_tl(t2, cpu_env, offsetof(CPUState, regs[R_EAX]));
5414 tcg_gen_ld_tl(cpu_T3, cpu_env, offsetof(CPUState, regs[R_ECX]));
6322 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
6325 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
6436 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
6440 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
6919 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector));
6942 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector));
6989 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
6992 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
7038 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
7041 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
7146 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base));
7147 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit));
7149 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base));
7150 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit));
7157 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]) + 4);
7159 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]));
7182 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,segs[R_GS].base));
7183 tcg_gen_ld_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,kernelgsbase));
7184 tcg_gen_st_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,segs[R_GS].base));
7185 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,kernelgsbase));
7403 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg]));
7477 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
7479 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
7583 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
