Lines Matching refs:CPUState
557 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
580 tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
597 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX]));
602 tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX]));
607 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX]));
612 tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX]));
618 tcg_gen_ld_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d));
633 tcg_gen_st_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d));
773 static inline void restore_cpu_state (CPUState *env, DisasContext *ctx)
871 static inline void check_insn(CPUState *env, DisasContext *ctx, int flags)
922 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
923 tcg_gen_st_tl(ret, cpu_env, offsetof(CPUState, llval)); \
949 tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
952 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
955 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, llreg)); \
956 tcg_gen_st_tl(arg1, cpu_env, offsetof(CPUState, llnewval)); \
1250 static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
1337 static void gen_logic_imm (CPUState *env, uint32_t opc, int rt, int rs, int16_t imm)
1379 static void gen_slt_imm (CPUState *env, uint32_t opc, int rt, int rs, int16_t imm)
1407 static void gen_shift_imm(CPUState *env, DisasContext *ctx, uint32_t opc,
1546 static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
1727 static void gen_cond_move (CPUState *env, uint32_t opc, int rd, int rs, int rt)
1764 static void gen_logic (CPUState *env, uint32_t opc, int rd, int rs, int rt)
1824 static void gen_slt (CPUState *env, uint32_t opc, int rd, int rs, int rt)
1855 static void gen_shift (CPUState *env, DisasContext *ctx, uint32_t opc,
2898 static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
2909 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Index));
2939 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEControl));
2944 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf0));
2949 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf1));
2954 gen_mfc0_load64(arg, offsetof(CPUState, CP0_YQMask));
2959 gen_mfc0_load64(arg, offsetof(CPUState, CP0_VPESchedule));
2964 gen_mfc0_load64(arg, offsetof(CPUState, CP0_VPEScheFBack));
2969 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEOpt));
2979 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo0));
3025 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo1));
3036 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_Context));
3051 gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageMask));
3056 gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageGrain));
3066 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Wired));
3071 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf0));
3076 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf1));
3081 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf2));
3086 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf3));
3091 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf4));
3102 gen_mfc0_load32(arg, offsetof(CPUState, CP0_HWREna));
3112 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_BadVAddr));
3141 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryHi));
3152 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Compare));
3163 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Status));
3168 gen_mfc0_load32(arg, offsetof(CPUState, CP0_IntCtl));
3173 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSCtl));
3178 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSMap));
3188 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Cause));
3198 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
3209 gen_mfc0_load32(arg, offsetof(CPUState, CP0_PRid));
3214 gen_mfc0_load32(arg, offsetof(CPUState, CP0_EBase));
3224 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config0));
3228 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config1));
3232 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config2));
3236 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config3));
3242 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config6));
3246 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config7));
3288 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_XContext));
3301 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Framemask));
3342 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
3353 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Performance0));
3408 gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagLo));
3415 gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataLo));
3428 gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagHi));
3435 gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataHi));
3445 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
3457 gen_mfc0_load32(arg, offsetof(CPUState, CP0_DESAVE));
3475 static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
3539 gen_mtc0_store64(arg, offsetof(CPUState, CP0_VPESchedule));
3544 gen_mtc0_store64(arg, offsetof(CPUState, CP0_VPEScheFBack));
3748 gen_mtc0_store32(arg, offsetof(CPUState, CP0_SRSMap));
3771 gen_mtc0_store64(arg, offsetof(CPUState, CP0_EPC));
3931 gen_mtc0_store64(arg, offsetof(CPUState, CP0_DEPC));
4034 gen_mtc0_store64(arg, offsetof(CPUState, CP0_ErrorEPC));
4045 gen_mtc0_store32(arg, offsetof(CPUState, CP0_DESAVE));
4071 static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
4082 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Index));
4112 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEControl));
4117 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf0));
4122 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf1));
4127 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_YQMask));
4132 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_VPESchedule));
4137 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
4142 gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEOpt));
4152 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo0));
4197 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo1));
4207 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_Context));
4221 gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageMask));
4226 gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageGrain));
4236 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Wired));
4241 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf0));
4246 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf1));
4251 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf2));
4256 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf3));
4261 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf4));
4272 gen_mfc0_load32(arg, offsetof(CPUState, CP0_HWREna));
4282 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_BadVAddr));
4310 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryHi));
4320 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Compare));
4331 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Status));
4336 gen_mfc0_load32(arg, offsetof(CPUState, CP0_IntCtl));
4341 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSCtl));
4346 gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSMap));
4356 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Cause));
4366 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
4376 gen_mfc0_load32(arg, offsetof(CPUState, CP0_PRid));
4381 gen_mfc0_load32(arg, offsetof(CPUState, CP0_EBase));
4391 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config0));
4395 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config1));
4399 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config2));
4403 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config3));
4408 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config6));
4412 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config7));
4453 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_XContext));
4464 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Framemask));
4505 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
4515 gen_mfc0_load32(arg, offsetof(CPUState, CP0_Performance0));
4571 gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagLo));
4578 gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataLo));
4591 gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagHi));
4598 gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataHi));
4608 tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
4619 gen_mfc0_load32(arg, offsetof(CPUState, CP0_DESAVE));
4637 static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
4701 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_VPESchedule));
4706 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
4914 gen_mtc0_store32(arg, offsetof(CPUState, CP0_SRSMap));
4937 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
5084 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
5187 tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
5198 gen_mtc0_store32(arg, offsetof(CPUState, CP0_DESAVE));
5224 static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd,
5388 static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt,
5552 static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int rd)
5675 static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
7628 static void decode_opc (CPUState *env, DisasContext *ctx)
7876 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, tls_value));
8279 gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
8422 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
8427 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
8432 static void fpu_dump_state(CPUState *env, FILE *f,
8474 cpu_mips_check_sign_extensions (CPUState *env, FILE *f,
8501 void cpu_dump_state (CPUState *env, FILE *f,
8542 offsetof(CPUState, active_tc.gpr[i]),
8545 offsetof(CPUState, active_tc.PC), "PC");
8548 offsetof(CPUState, active_tc.HI[i]),
8551 offsetof(CPUState, active_tc.LO[i]),
8554 offsetof(CPUState, active_tc.ACX[i]),
8558 offsetof(CPUState, active_tc.DSPControl),
8561 offsetof(CPUState, bcond), "bcond");
8563 offsetof(CPUState, btarget), "btarget");
8565 offsetof(CPUState, hflags), "hflags");
8568 offsetof(CPUState, active_fpu.fcr0),
8571 offsetof(CPUState, active_fpu.fcr31),
8710 void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
