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50 #define MIPS_FCR0 ((0 << FCR0_S) | (0x1 << FCR0_PRID) | (0x10 << FCR0_REV))
182         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
202         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
222         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
243         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
266         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
314         .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
333         .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
424         .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
540 //                             (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
553                              (0x1 << CP0MVPC1_PCP1);