Lines Matching refs:shift_imm
183 Operand::Operand(Register rm, ShiftOp shift_op, int shift_imm) {
184 ASSERT(is_uint5(shift_imm));
185 ASSERT(shift_op != ROR || shift_imm != 0); // use RRX if you mean it
189 shift_imm_ = shift_imm & 31;
191 // encoded as ROR with shift_imm == 0
192 ASSERT(shift_imm == 0);
225 ShiftOp shift_op, int shift_imm, AddrMode am) {
226 ASSERT(is_uint5(shift_imm));
230 shift_imm_ = shift_imm & 31;
