Lines Matching refs:destination
77 // the same as the destination, the destination is ignored and
98 // its destination. All other moves from the spilled source have been
106 // Clear this move's destination to indicate a pending move. The actual
107 // destination is saved in a stack allocated local. Multiple moves can
110 LOperand* destination = moves_[index].destination();
115 // as this one's destination blocks this one so recursively perform all
119 if (other_move.Blocks(destination) && !other_move.IsPending()) {
128 // pending, so restore its destination.
129 moves_[index].set_destination(destination);
135 if (other_move.Blocks(destination)) {
148 // No operand should be the destination for more than one move.
150 LOperand* destination = moves_[i].destination();
152 SLOW_ASSERT(!destination->Equals(moves_[j].destination()));
164 ASSERT(moves_[index].destination()->Equals(moves_[root_index_].source()));
168 saved_destination_ = moves_[index].destination();
180 // This move will be done by restoring the saved value to the destination.
209 LOperand* destination = moves_[index].destination();
211 // Dispatch on the source and destination operand kinds. Not all
216 if (destination->IsRegister()) {
217 __ mov(cgen_->ToRegister(destination), source_register);
219 ASSERT(destination->IsStackSlot());
220 __ str(source_register, cgen_->ToMemOperand(destination));
225 if (destination->IsRegister()) {
226 __ ldr(cgen_->ToRegister(destination), source_operand);
228 ASSERT(destination->IsStackSlot());
229 MemOperand destination_operand = cgen_->ToMemOperand(destination);
232 // ip is overwritten while saving the value to the destination.
249 if (destination->IsRegister()) {
250 Register dst = cgen_->ToRegister(destination);
257 ASSERT(destination->IsStackSlot());
266 __ str(kSavedValueRegister, cgen_->ToMemOperand(destination));
271 if (destination->IsDoubleRegister()) {
272 __ vmov(cgen_->ToDoubleRegister(destination), source_register);
274 ASSERT(destination->IsDoubleStackSlot());
275 __ vstr(source_register, cgen_->ToMemOperand(destination));
280 if (destination->IsDoubleRegister()) {
281 __ vldr(cgen_->ToDoubleRegister(destination), source_operand);
283 ASSERT(destination->IsDoubleStackSlot());
284 MemOperand destination_operand = cgen_->ToMemOperand(destination);
291 cgen_->ToHighMemOperand(destination);
