Lines Matching defs:rd
2011 // Raw field decoding here. Multiply instructions have their Rd in
2020 // The MUL instruction description (A 4.1.33) refers to Rd as being
2024 int rd = rn; // Remap the rn field to the Rd register.
2026 set_register(rd, alu_out);
2032 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
2033 // Rn field to encode the Rd register and the Rd field to encode
2035 Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
2040 // and Rd fields as follows:
2041 // RdLo == Rd
2042 // RdHi == Rn (This is confusingly stored in variable rd here
2044 // Rn field to encode the Rd register. Good luck figuring
2047 // Format(instr, "'um'al'cond's 'rd, 'rn, 'rs, 'rm");
2077 int rd = instr->RdValue();
2086 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], -'rm");
2094 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], +'rm");
2102 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, -'rm]'w");
2111 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, +'rm]'w");
2129 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], #-'off8");
2137 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], #+'off8");
2145 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, #-'off8]'w");
2154 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, #+'off8]'w");
2170 ASSERT((rd % 2) == 0);
2173 int32_t value1 = get_register(rd);
2174 int32_t value2 = get_register(rd+1);
2179 set_dw_register(rd, rn_data);
2185 set_register(rd, val);
2187 int16_t val = get_register(rd);
2193 set_register(rd, val);
2195 uint16_t val = get_register(rd);
2204 set_register(rd, val);
2232 int rd = instr->RdValue();
2245 set_register(rd, leading_zeros);
2256 int rd = instr->RdValue();
2271 // Format(instr, "and'cond's 'rd, 'rn, 'shift_rm");
2272 // Format(instr, "and'cond's 'rd, 'rn, 'imm");
2274 set_register(rd, alu_out);
2283 // Format(instr, "eor'cond's 'rd, 'rn, 'shift_rm");
2284 // Format(instr, "eor'cond's 'rd, 'rn, 'imm");
2286 set_register(rd, alu_out);
2295 // Format(instr, "sub'cond's 'rd, 'rn, 'shift_rm");
2296 // Format(instr, "sub'cond's 'rd, 'rn, 'imm");
2298 set_register(rd, alu_out);
2308 // Format(instr, "rsb'cond's 'rd, 'rn, 'shift_rm");
2309 // Format(instr, "rsb'cond's 'rd, 'rn, 'imm");
2311 set_register(rd, alu_out);
2321 // Format(instr, "add'cond's 'rd, 'rn, 'shift_rm");
2322 // Format(instr, "add'cond's 'rd, 'rn, 'imm");
2324 set_register(rd, alu_out);
2334 // Format(instr, "adc'cond's 'rd, 'rn, 'shift_rm");
2335 // Format(instr, "adc'cond's 'rd, 'rn, 'imm");
2337 set_register(rd, alu_out);
2347 Format(instr, "sbc'cond's 'rd, 'rn, 'shift_rm");
2348 Format(instr, "sbc'cond's 'rd, 'rn, 'imm");
2353 Format(instr, "rsc'cond's 'rd, 'rn, 'shift_rm");
2354 Format(instr, "rsc'cond's 'rd, 'rn, 'imm");
2366 // Format(instr, "movw'cond 'rd, 'imm").
2368 set_register(rd, alu_out);
2397 // Format(instr, "movt'cond 'rd, 'imm").
2398 alu_out = (get_register(rd) & 0xffff) |
2400 set_register(rd, alu_out);
2422 // Format(instr, "orr'cond's 'rd, 'rn, 'shift_rm");
2423 // Format(instr, "orr'cond's 'rd, 'rn, 'imm");
2425 set_register(rd, alu_out);
2434 // Format(instr, "mov'cond's 'rd, 'shift_rm");
2435 // Format(instr, "mov'cond's 'rd, 'imm");
2437 set_register(rd, alu_out);
2446 // Format(instr, "bic'cond's 'rd, 'rn, 'shift_rm");
2447 // Format(instr, "bic'cond's 'rd, 'rn, 'imm");
2449 set_register(rd, alu_out);
2458 // Format(instr, "mvn'cond's 'rd, 'shift_rm");
2459 // Format(instr, "mvn'cond's 'rd, 'imm");
2461 set_register(rd, alu_out);
2479 int rd = instr->RdValue();
2486 // Format(instr, "'memop'cond'b 'rd, ['rn], #-'off12");
2494 // Format(instr, "'memop'cond'b 'rd, ['rn], #+'off12");
2502 // Format(instr, "'memop'cond'b 'rd, ['rn, #-'off12]'w");
2511 // Format(instr, "'memop'cond'b 'rd, ['rn, #+'off12]'w");
2527 set_register(rd, val);
2529 byte val = get_register(rd);
2534 set_register(rd, ReadW(addr, instr));
2536 WriteW(addr, get_register(rd), instr);
2543 int rd = instr->RdValue();
2552 Format(instr, "'memop'cond'b 'rd, ['rn], -'shift_rm");
2579 set_register(rd, rm_val);
2585 Format(instr, "'memop'cond'b 'rd, ['rn], +'shift_rm");
2591 // Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w");
2645 // Format(instr, "'memop'cond'b 'rd, ['rn, +'shift_rm]'w");
2661 set_register(rd, byte);
2663 uint8_t byte = get_register(rd);
2668 set_register(rd, ReadW(addr, instr));
2670 WriteW(addr, get_register(rd), instr);
