Lines Matching full:instruction
59 void Stop(Instruction* instr);
77 bool SetBreakpoint(Instruction* breakpc);
78 bool DeleteBreakpoint(Instruction* breakpc);
104 void ArmDebugger::Stop(Instruction* instr) {
109 reinterpret_cast<char**>(sim_->get_pc() + Instruction::kInstrSize);
123 // Overwrite the instruction and address with nops.
125 reinterpret_cast<Instruction*>(msg_address)->SetInstructionBits(kNopInstr);
127 sim_->set_pc(sim_->get_pc() + 2 * Instruction::kInstrSize);
136 void ArmDebugger::Stop(Instruction* instr) {
141 + Instruction::kInstrSize);
152 sim_->set_pc(sim_->get_pc() + 2 * Instruction::kInstrSize);
215 bool ArmDebugger::SetBreakpoint(Instruction* breakpc) {
224 // Not setting the breakpoint instruction in the code itself. It will be set
230 bool ArmDebugger::DeleteBreakpoint(Instruction* breakpc) {
309 sim_->InstructionDecode(reinterpret_cast<Instruction*>(sim_->get_pc()));
311 // Execute the one instruction we broke at with breakpoints disabled.
312 sim_->InstructionDecode(reinterpret_cast<Instruction*>(sim_->get_pc()));
438 end = cur + (10 * Instruction::kInstrSize);
447 end = cur + (10 * Instruction::kInstrSize);
455 end = cur + (value * Instruction::kInstrSize);
463 end = cur + (value2 * Instruction::kInstrSize);
481 if (!SetBreakpoint(reinterpret_cast<Instruction*>(value))) {
506 intptr_t stop_pc = sim_->get_pc() - 2 * Instruction::kInstrSize;
507 Instruction* stop_instr = reinterpret_cast<Instruction*>(stop_pc);
508 Instruction* msg_address =
509 reinterpret_cast<Instruction*>(stop_pc + Instruction::kInstrSize);
565 PrintF(" step one instruction (alias 'si')\n");
610 PrintF(" ignore the stop instruction at the current location\n");
707 Instruction* instr) {
720 Instruction::kInstrSize) == 0);
800 // reference to a svc (Supervisor Call) instruction that is handled by
802 // offset from the svc instruction so the simulator knows what to call.
815 Instruction::kInstrSize);
836 static Redirection* FromSwiInstruction(Instruction* swi_instruction) {
893 return registers_[reg] + ((reg == pc) ? Instruction::kPCReadOffset : 0);
1110 int Simulator::ReadW(int32_t addr, Instruction* instr) {
1128 void Simulator::WriteW(int32_t addr, int value, Instruction* instr) {
1147 uint16_t Simulator::ReadHU(int32_t addr, Instruction* instr) {
1165 int16_t Simulator::ReadH(int32_t addr, Instruction* instr) {
1181 void Simulator::WriteH(int32_t addr, uint16_t value, Instruction* instr) {
1200 void Simulator::WriteH(int32_t addr, int16_t value, Instruction* instr) {
1287 void Simulator::Format(Instruction* instr, const char* format) {
1288 PrintF("Simulator found unsupported instruction:\n 0x%08x: %s\n",
1294 // Checks if the current instruction should be executed based on its
1296 bool Simulator::ConditionallyExecute(Instruction* instr) {
1415 int32_t Simulator::GetShiftRm(Instruction* instr, bool* carry_out) {
1559 int32_t Simulator::GetImm(Instruction* instr, bool* carry_out) {
1580 void Simulator::ProcessPUW(Instruction* instr,
1621 void Simulator::HandleRList(Instruction* instr, bool load) {
1650 void Simulator::HandleVList(Instruction* instr) {
1727 void Simulator::SoftwareInterrupt(Instruction* instr) {
1917 set_pc(get_pc() + 2 * Instruction::kInstrSize);
1930 bool Simulator::isStopInstruction(Instruction* instr) {
2001 // Handle execution based on instruction types.
2003 Instruction types 0 and 1 are both rolled into one function because they
2005 void Simulator::DecodeType01(Instruction* instr) {
2008 // multiply instruction or extra loads and stores
2020 // The MUL instruction description (A 4.1.33) refers to Rd as being
2031 // The MLA instruction description (A 4.1.28) refers to the order
2043 // because the mul instruction from above uses the
2045 // this out without reading the ARM instruction manual
2172 // The strd instruction.
2177 // The ldrd instruction.
2218 set_register(lr, old_pc + Instruction::kInstrSize);
2478 void Simulator::DecodeType2(Instruction* instr) {
2542 void Simulator::DecodeType3(Instruction* instr) {
2572 // There is no Q flag yet, and no instruction (MRS) to read the
2676 void Simulator::DecodeType4(Instruction* instr) {
2688 void Simulator::DecodeType5(Instruction* instr) {
2693 set_register(lr, pc_address + Instruction::kInstrSize);
2700 void Simulator::DecodeType6(Instruction* instr) {
2705 void Simulator::DecodeType7(Instruction* instr) {
2714 // void Simulator::DecodeTypeVFP(Instruction* instr)
2729 void Simulator::DecodeTypeVFP(Instruction* instr) {
2885 Instruction* instr) {
2903 void Simulator::DecodeVCMP(Instruction* instr) {
2941 void Simulator::DecodeVCVTBetweenDoubleAndSingle(Instruction* instr) {
3019 void Simulator::DecodeVCVTBetweenFloatingPointAndInteger(Instruction* instr) {
3123 // void Simulator::DecodeType6CoprocessorIns(Instruction* instr)
3129 void Simulator::DecodeType6CoprocessorIns(Instruction* instr) {
3227 // Executes the current instruction.
3228 void Simulator::InstructionDecode(Instruction* instr) {
3280 // If the instruction is a non taken conditional stop, we need to skip the
3283 set_pc(get_pc() + 2 * Instruction::kInstrSize);
3287 + Instruction::kInstrSize);
3299 // should be stopping at a particular executed instruction.
3301 Instruction* instr = reinterpret_cast<Instruction*>(program_counter);
3310 Instruction* instr = reinterpret_cast<Instruction*>(program_counter);
