Lines Matching refs:instr
59 void Stop(Instruction* instr);
63 static const Instr kBreakpointInstr =
65 static const Instr kNopInstr = (al | (13*B21));
104 void ArmDebugger::Stop(Instruction* instr) {
106 uint32_t code = instr->SvcValue() & kStopCodeMask;
124 instr->SetInstructionBits(kNopInstr);
136 void ArmDebugger::Stop(Instruction* instr) {
138 uint32_t code = instr->SvcValue() & kStopCodeMask;
707 Instruction* instr) {
708 intptr_t address = reinterpret_cast<intptr_t>(instr);
718 CHECK(memcmp(reinterpret_cast<void*>(instr),
1110 int Simulator::ReadW(int32_t addr, Instruction* instr) {
1121 reinterpret_cast<intptr_t>(instr));
1128 void Simulator::WriteW(int32_t addr, int value, Instruction* instr) {
1141 reinterpret_cast<intptr_t>(instr));
1147 uint16_t Simulator::ReadHU(int32_t addr, Instruction* instr) {
1158 reinterpret_cast<intptr_t>(instr));
1165 int16_t Simulator::ReadH(int32_t addr, Instruction* instr) {
1181 void Simulator::WriteH(int32_t addr, uint16_t value, Instruction* instr) {
1194 reinterpret_cast<intptr_t>(instr));
1200 void Simulator::WriteH(int32_t addr, int16_t value, Instruction* instr) {
1213 reinterpret_cast<intptr_t>(instr));
1287 void Simulator::Format(Instruction* instr, const char* format) {
1289 reinterpret_cast<intptr_t>(instr), format);
1296 bool Simulator::ConditionallyExecute(Instruction* instr) {
1297 switch (instr->ConditionField()) {
1415 int32_t Simulator::GetShiftRm(Instruction* instr, bool* carry_out) {
1416 ShiftOp shift = instr->ShiftField();
1417 int shift_amount = instr->ShiftAmountValue();
1418 int32_t result = get_register(instr->RmValue());
1419 if (instr->Bit(4) == 0) {
1482 int rs = instr->RsValue();
1559 int32_t Simulator::GetImm(Instruction* instr, bool* carry_out) {
1560 int rotate = instr->RotateValue() * 2;
1561 int immed8 = instr->Immed8Value();
1580 void Simulator::ProcessPUW(Instruction* instr,
1585 int rn = instr->RnValue();
1587 switch (instr->PUField()) {
1615 if (instr->HasW()) {
1621 void Simulator::HandleRList(Instruction* instr, bool load) {
1622 int rlist = instr->RlistValue();
1627 ProcessPUW(instr, num_regs, kPointerSize, &start_address, &end_address);
1650 void Simulator::HandleVList(Instruction* instr) {
1652 (instr->SzValue() == 0) ? kSinglePrecision : kDoublePrecision;
1655 bool load = (instr->VLValue() == 0x1);
1659 vd = instr->VFPDRegValue(precision);
1661 num_regs = instr->Immed8Value();
1663 num_regs = instr->Immed8Value() / 2;
1668 ProcessPUW(instr, num_regs, operand_size, &start_address, &end_address);
1675 reg, ReadW(reinterpret_cast<int32_t>(address), instr));
1678 get_sinteger_from_s_register(reg), instr);
1684 2 * reg, ReadW(reinterpret_cast<int32_t>(address), instr));
1686 2 * reg + 1, ReadW(reinterpret_cast<int32_t>(address + 1), instr));
1689 get_sinteger_from_s_register(2 * reg), instr);
1691 get_sinteger_from_s_register(2 * reg + 1), instr);
1727 void Simulator::SoftwareInterrupt(Instruction* instr) {
1728 int svc = instr->SvcValue();
1736 Redirection* redirection = Redirection::FromSwiInstruction(instr);
1915 dbg.Stop(instr);
1930 bool Simulator::isStopInstruction(Instruction* instr) {
1931 return (instr->Bits(27, 24) == 0xF) && (instr->SvcValue() >= kStopCode);
2005 void Simulator::DecodeType01(Instruction* instr) {
2006 int type = instr->TypeValue();
2007 if ((type == 0) && instr->IsSpecialType0()) {
2009 if (instr->Bits(7, 4) == 9) {
2010 if (instr->Bit(24) == 0) {
2013 int rn = instr->RnValue();
2014 int rm = instr->RmValue();
2015 int rs = instr->RsValue();
2018 if (instr->Bit(23) == 0) {
2019 if (instr->Bit(21) == 0) {
2023 // Format(instr, "mul'cond's 'rn, 'rm, 'rs");
2027 if (instr->HasS()) {
2035 Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
2047 // Format(instr, "'um'al'cond's 'rd, 'rn, 'rs, 'rm");
2049 int rd_lo = instr->RdValue();
2052 if (instr->Bit(22) == 1) {
2068 if (instr->HasS()) {
2077 int rd = instr->RdValue();
2078 int rn = instr->RnValue();
2081 if (instr->Bit(22) == 0) {
2082 int rm = instr->RmValue();
2084 switch (instr->PUField()) {
2086 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], -'rm");
2087 ASSERT(!instr->HasW());
2094 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], +'rm");
2095 ASSERT(!instr->HasW());
2102 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, -'rm]'w");
2105 if (instr->HasW()) {
2111 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, +'rm]'w");
2114 if (instr->HasW()) {
2126 int32_t imm_val = (instr->ImmedHValue() << 4) | instr->ImmedLValue();
2127 switch (instr->PUField()) {
2129 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], #-'off8");
2130 ASSERT(!instr->HasW());
2137 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], #+'off8");
2138 ASSERT(!instr->HasW());
2145 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, #-'off8]'w");
2148 if (instr->HasW()) {
2154 // Format(instr, "'memop'cond'sign'h 'rd, ['rn, #+'off8]'w");
2157 if (instr->HasW()) {
2169 if (((instr->Bits(7, 4) & 0xd) == 0xd) && (instr->Bit(20) == 0)) {
2171 if (instr->HasH()) {
2181 } else if (instr->HasH()) {
2182 if (instr->HasSign()) {
2183 if (instr->HasL()) {
2184 int16_t val = ReadH(addr, instr);
2188 WriteH(addr, val, instr);
2191 if (instr->HasL()) {
2192 uint16_t val = ReadHU(addr, instr);
2196 WriteH(addr, val, instr);
2201 ASSERT(instr->HasSign());
2202 ASSERT(instr->HasL());
2208 } else if ((type == 0) && instr->IsMiscType0()) {
2209 if (instr->Bits(22, 21) == 1) {
2210 int rm = instr->RmValue();
2211 switch (instr->BitField(7, 4)) {
2230 } else if (instr->Bits(22, 21) == 3) {
2231 int rm = instr->RmValue();
2232 int rd = instr->RdValue();
2233 switch (instr->BitField(7, 4)) {
2252 PrintF("%08x\n", instr->InstructionBits());
2256 int rd = instr->RdValue();
2257 int rn = instr->RnValue();
2262 shifter_operand = GetShiftRm(instr, &shifter_carry_out);
2264 ASSERT(instr->TypeValue() == 1);
2265 shifter_operand = GetImm(instr, &shifter_carry_out);
2269 switch (instr->OpcodeField()) {
2271 // Format(instr, "and'cond's 'rd, 'rn, 'shift_rm");
2272 // Format(instr, "and'cond's 'rd, 'rn, 'imm");
2275 if (instr->HasS()) {
2283 // Format(instr, "eor'cond's 'rd, 'rn, 'shift_rm");
2284 // Format(instr, "eor'cond's 'rd, 'rn, 'imm");
2287 if (instr->HasS()) {
2295 // Format(instr, "sub'cond's 'rd, 'rn, 'shift_rm");
2296 // Format(instr, "sub'cond's 'rd, 'rn, 'imm");
2299 if (instr->HasS()) {
2308 // Format(instr, "rsb'cond's 'rd, 'rn, 'shift_rm");
2309 // Format(instr, "rsb'cond's 'rd, 'rn, 'imm");
2312 if (instr->HasS()) {
2321 // Format(instr, "add'cond's 'rd, 'rn, 'shift_rm");
2322 // Format(instr, "add'cond's 'rd, 'rn, 'imm");
2325 if (instr->HasS()) {
2334 // Format(instr, "adc'cond's 'rd, 'rn, 'shift_rm");
2335 // Format(instr, "adc'cond's 'rd, 'rn, 'imm");
2338 if (instr->HasS()) {
2347 Format(instr, "sbc'cond's 'rd, 'rn, 'shift_rm");
2348 Format(instr, "sbc'cond's 'rd, 'rn, 'imm");
2353 Format(instr, "rsc'cond's 'rd, 'rn, 'shift_rm");
2354 Format(instr, "rsc'cond's 'rd, 'rn, 'imm");
2359 if (instr->HasS()) {
2360 // Format(instr, "tst'cond 'rn, 'shift_rm");
2361 // Format(instr, "tst'cond 'rn, 'imm");
2366 // Format(instr, "movw'cond 'rd, 'imm").
2367 alu_out = instr->ImmedMovwMovtValue();
2374 if (instr->HasS()) {
2375 // Format(instr, "teq'cond 'rn, 'shift_rm");
2376 // Format(instr, "teq'cond 'rn, 'imm");
2389 if (instr->HasS()) {
2390 // Format(instr, "cmp'cond 'rn, 'shift_rm");
2391 // Format(instr, "cmp'cond 'rn, 'imm");
2397 // Format(instr, "movt'cond 'rd, 'imm").
2399 (instr->ImmedMovwMovtValue() << 16);
2406 if (instr->HasS()) {
2407 // Format(instr, "cmn'cond 'rn, 'shift_rm");
2408 // Format(instr, "cmn'cond 'rn, 'imm");
2422 // Format(instr, "orr'cond's 'rd, 'rn, 'shift_rm");
2423 // Format(instr, "orr'cond's 'rd, 'rn, 'imm");
2426 if (instr->HasS()) {
2434 // Format(instr, "mov'cond's 'rd, 'shift_rm");
2435 // Format(instr, "mov'cond's 'rd, 'imm");
2438 if (instr->HasS()) {
2446 // Format(instr, "bic'cond's 'rd, 'rn, 'shift_rm");
2447 // Format(instr, "bic'cond's 'rd, 'rn, 'imm");
2450 if (instr->HasS()) {
2458 // Format(instr, "mvn'cond's 'rd, 'shift_rm");
2459 // Format(instr, "mvn'cond's 'rd, 'imm");
2462 if (instr->HasS()) {
2478 void Simulator::DecodeType2(Instruction* instr) {
2479 int rd = instr->RdValue();
2480 int rn = instr->RnValue();
2482 int32_t im_val = instr->Offset12Value();
2484 switch (instr->PUField()) {
2486 // Format(instr, "'memop'cond'b 'rd, ['rn], #-'off12");
2487 ASSERT(!instr->HasW());
2494 // Format(instr, "'memop'cond'b 'rd, ['rn], #+'off12");
2495 ASSERT(!instr->HasW());
2502 // Format(instr, "'memop'cond'b 'rd, ['rn, #-'off12]'w");
2505 if (instr->HasW()) {
2511 // Format(instr, "'memop'cond'b 'rd, ['rn, #+'off12]'w");
2514 if (instr->HasW()) {
2524 if (instr->HasB()) {
2525 if (instr->HasL()) {
2533 if (instr->HasL()) {
2534 set_register(rd, ReadW(addr, instr));
2536 WriteW(addr, get_register(rd), instr);
2542 void Simulator::DecodeType3(Instruction* instr) {
2543 int rd = instr->RdValue();
2544 int rn = instr->RnValue();
2547 int32_t shifter_operand = GetShiftRm(instr, &shifter_carry_out);
2549 switch (instr->PUField()) {
2551 ASSERT(!instr->HasW());
2552 Format(instr, "'memop'cond'b 'rd, ['rn], -'shift_rm");
2557 if (instr->HasW()) {
2558 ASSERT(instr->Bits(5, 4) == 0x1);
2560 if (instr->Bit(22) == 0x1) { // USAT.
2561 int32_t sat_pos = instr->Bits(20, 16);
2563 int32_t shift = instr->Bits(11, 7);
2564 int32_t shift_type = instr->Bit(6);
2565 int32_t rm_val = get_register(instr->RmValue());
2585 Format(instr, "'memop'cond'b 'rd, ['rn], +'shift_rm");
2591 // Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w");
2593 if (instr->HasW()) {
2599 if (instr->HasW() && (instr->Bits(6, 4) == 0x5)) {
2600 uint32_t widthminus1 = static_cast<uint32_t>(instr->Bits(20, 16));
2601 uint32_t lsbit = static_cast<uint32_t>(instr->Bits(11, 7));
2604 if (instr->Bit(22)) {
2607 static_cast<uint32_t>(get_register(instr->RmValue()));
2610 set_register(instr->RdValue(), extr_val);
2613 int32_t rm_val = get_register(instr->RmValue());
2616 set_register(instr->RdValue(), extr_val);
2622 } else if (!instr->HasW() && (instr->Bits(6, 4) == 0x1)) {
2623 uint32_t lsbit = static_cast<uint32_t>(instr->Bits(11, 7));
2624 uint32_t msbit = static_cast<uint32_t>(instr->Bits(20, 16));
2628 static_cast<uint32_t>(get_register(instr->RdValue()));
2632 if (instr->RmValue() != 15) {
2635 static_cast<uint32_t>(get_register(instr->RmValue()));
2639 set_register(instr->RdValue(), rd_val);
2645 // Format(instr, "'memop'cond'b 'rd, ['rn, +'shift_rm]'w");
2647 if (instr->HasW()) {
2658 if (instr->HasB()) {
2659 if (instr->HasL()) {
2667 if (instr->HasL()) {
2668 set_register(rd, ReadW(addr, instr));
2670 WriteW(addr, get_register(rd), instr);
2676 void Simulator::DecodeType4(Instruction* instr) {
2677 ASSERT(instr->Bit(22) == 0); // only allowed to be set in privileged mode
2678 if (instr->HasL()) {
2679 // Format(instr, "ldm'cond'pu 'rn'w, 'rlist");
2680 HandleRList(instr, true);
2682 // Format(instr, "stm'cond'pu 'rn'w, 'rlist");
2683 HandleRList(instr, false);
2688 void Simulator::DecodeType5(Instruction* instr) {
2689 // Format(instr, "b'l'cond 'target");
2690 int off = (instr->SImmed24Value() << 2);
2692 if (instr->HasLink()) {
2700 void Simulator::DecodeType6(Instruction* instr) {
2701 DecodeType6CoprocessorIns(instr);
2705 void Simulator::DecodeType7(Instruction* instr) {
2706 if (instr->Bit(24) == 1) {
2707 SoftwareInterrupt(instr);
2709 DecodeTypeVFP(instr);
2714 // void Simulator::DecodeTypeVFP(Instruction* instr)
2729 void Simulator::DecodeTypeVFP(Instruction* instr) {
2730 ASSERT((instr->TypeValue() == 7) && (instr->Bit(24) == 0x0) );
2731 ASSERT(instr->Bits(11, 9) == 0x5);
2734 int vm = instr->VFPMRegValue(kDoublePrecision);
2735 int vd = instr->VFPDRegValue(kDoublePrecision);
2736 int vn = instr->VFPNRegValue(kDoublePrecision);
2738 if (instr->Bit(4) == 0) {
2739 if (instr->Opc1Value() == 0x7) {
2741 if ((instr->Opc2Value() == 0x0) && (instr->Opc3Value() == 0x1)) {
2743 if (instr->SzValue() == 0x1) {
2744 int m = instr->VFPMRegValue(kDoublePrecision);
2745 int d = instr->VFPDRegValue(kDoublePrecision);
2748 int m = instr->VFPMRegValue(kSinglePrecision);
2749 int d = instr->VFPDRegValue(kSinglePrecision);
2752 } else if ((instr->Opc2Value() == 0x0) && (instr->Opc3Value() == 0x3)) {
2757 } else if ((instr->Opc2Value() == 0x1) && (instr->Opc3Value() == 0x1)) {
2762 } else if ((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3)) {
2763 DecodeVCVTBetweenDoubleAndSingle(instr);
2764 } else if ((instr->Opc2Value() == 0x8) && (instr->Opc3Value() & 0x1)) {
2765 DecodeVCVTBetweenFloatingPointAndInteger(instr);
2766 } else if (((instr->Opc2Value() >> 1) == 0x6) &&
2767 (instr->Opc3Value() & 0x1)) {
2768 DecodeVCVTBetweenFloatingPointAndInteger(instr);
2769 } else if (((instr->Opc2Value() == 0x4) || (instr->Opc2Value() == 0x5)) &&
2770 (instr->Opc3Value() & 0x1)) {
2771 DecodeVCMP(instr);
2772 } else if (((instr->Opc2Value() == 0x1)) && (instr->Opc3Value() == 0x3)) {
2777 } else if (instr->Opc3Value() == 0x0) {
2779 if (instr->SzValue() == 0x1) {
2780 set_d_register_from_double(vd, instr->DoubleImmedVmov());
2787 } else if (instr->Opc1Value() == 0x3) {
2788 if (instr->SzValue() != 0x1) {
2792 if (instr->Opc3Value() & 0x1) {
2805 } else if ((instr->Opc1Value() == 0x2) && !(instr->Opc3Value() & 0x1)) {
2807 if (instr->SzValue() != 0x1) {
2815 } else if ((instr->Opc1Value() == 0x4) && !(instr->Opc3Value() & 0x1)) {
2817 if (instr->SzValue() != 0x1) {
2830 if ((instr->VCValue() == 0x0) &&
2831 (instr->VAValue() == 0x0)) {
2832 DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(instr);
2833 } else if ((instr->VLValue() == 0x1) &&
2834 (instr->VCValue() == 0x0) &&
2835 (instr->VAValue() == 0x7) &&
2836 (instr->Bits(19, 16) == 0x1)) {
2838 uint32_t rt = instr->RtValue();
2855 } else if ((instr->VLValue() == 0x0) &&
2856 (instr->VCValue() == 0x0) &&
2857 (instr->VAValue() == 0x7) &&
2858 (instr->Bits(19, 16) == 0x1)) {
2860 uint32_t rt = instr->RtValue();
2885 Instruction* instr) {
2886 ASSERT((instr->Bit(4) == 1) && (instr->VCValue() == 0x0) &&
2887 (instr->VAValue() == 0x0));
2889 int t = instr->RtValue();
2890 int n = instr->VFPNRegValue(kSinglePrecision);
2891 bool to_arm_register = (instr->VLValue() == 0x1);
2903 void Simulator::DecodeVCMP(Instruction* instr) {
2904 ASSERT((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
2905 ASSERT(((instr->Opc2Value() == 0x4) || (instr->Opc2Value() == 0x5)) &&
2906 (instr->Opc3Value() & 0x1));
2910 if (instr->SzValue() == 1) {
2914 int d = instr->VFPDRegValue(precision);
2916 if (instr->Opc2Value() == 0x4) {
2917 m = instr->VFPMRegValue(precision);
2923 if (instr->Opc2Value() == 0x4) {
2928 if (instr->Bit(7) == 1) {
2941 void Simulator::DecodeVCVTBetweenDoubleAndSingle(Instruction* instr) {
2942 ASSERT((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7));
2943 ASSERT((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3));
2947 if (instr->SzValue() == 1) {
2952 int dst = instr->VFPDRegValue(dst_precision);
2953 int src = instr->VFPMRegValue(src_precision);
3019 void Simulator::DecodeVCVTBetweenFloatingPointAndInteger(Instruction* instr) {
3020 ASSERT((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7) &&
3021 (instr->Bits(27, 23) == 0x1D));
3022 ASSERT(((instr->Opc2Value() == 0x8) && (instr->Opc3Value() & 0x1)) ||
3023 (((instr->Opc2Value() >> 1) == 0x6) && (instr->Opc3Value() & 0x1)));
3026 bool to_integer = (instr->Bit(18) == 1);
3028 VFPRegPrecision src_precision = (instr->SzValue() == 1) ? kDoublePrecision
3039 int dst = instr->VFPDRegValue(kSinglePrecision);
3040 int src = instr->VFPMRegValue(src_precision);
3044 VFPRoundingMode mode = (instr->Bit(7) != 1) ? FPSCR_rounding_mode_
3048 bool unsigned_integer = (instr->Bit(16) == 0);
3097 bool unsigned_integer = (instr->Bit(7) == 0);
3099 int dst = instr->VFPDRegValue(src_precision);
3100 int src = instr->VFPMRegValue(kSinglePrecision);
3123 // void Simulator::DecodeType6CoprocessorIns(Instruction* instr)
3129 void Simulator::DecodeType6CoprocessorIns(Instruction* instr) {
3130 ASSERT((instr->TypeValue() == 6));
3132 if (instr->CoprocessorValue() == 0xA) {
3133 switch (instr->OpcodeValue()) {
3138 int rn = instr->RnValue();
3139 int vd = instr->VFPDRegValue(kSinglePrecision);
3140 int offset = instr->Immed8Value();
3141 if (!instr->HasU()) {
3146 if (instr->HasL()) {
3148 set_s_register_from_sinteger(vd, ReadW(address, instr));
3151 WriteW(address, get_sinteger_from_s_register(vd), instr);
3162 HandleVList(instr);
3167 } else if (instr->CoprocessorValue() == 0xB) {
3168 switch (instr->OpcodeValue()) {
3171 if (instr->Bits(7, 4) != 0x1) {
3174 int rt = instr->RtValue();
3175 int rn = instr->RnValue();
3176 int vm = instr->VmValue();
3177 if (instr->HasL()) {
3194 int rn = instr->RnValue();
3195 int vd = instr->VdValue();
3196 int offset = instr->Immed8Value();
3197 if (!instr->HasU()) {
3201 if (instr->HasL()) {
3203 set_s_register_from_sinteger(2*vd, ReadW(address, instr));
3204 set_s_register_from_sinteger(2*vd + 1, ReadW(address + 4, instr));
3207 WriteW(address, get_sinteger_from_s_register(2*vd), instr);
3208 WriteW(address + 4, get_sinteger_from_s_register(2*vd + 1), instr);
3216 HandleVList(instr);
3228 void Simulator::InstructionDecode(Instruction* instr) {
3230 CheckICache(isolate_->simulator_i_cache(), instr);
3239 reinterpret_cast<byte*>(instr));
3240 PrintF(" 0x%08x %s\n", reinterpret_cast<intptr_t>(instr), buffer.start());
3242 if (instr->ConditionField() == kSpecialCondition) {
3244 } else if (ConditionallyExecute(instr)) {
3245 switch (instr->TypeValue()) {
3248 DecodeType01(instr);
3252 DecodeType2(instr);
3256 DecodeType3(instr);
3260 DecodeType4(instr);
3264 DecodeType5(instr);
3268 DecodeType6(instr);
3272 DecodeType7(instr);
3282 } else if (instr->IsStop()) {
3286 set_register(pc, reinterpret_cast<int32_t>(instr)
3301 Instruction* instr = reinterpret_cast<Instruction*>(program_counter);
3303 InstructionDecode(instr);
3310 Instruction* instr = reinterpret_cast<Instruction*>(program_counter);
3316 InstructionDecode(instr);
