Lines Matching defs:rd
378 Register rd;
379 rd.code_ = (instr & kRdFieldMask) >> kRdShift;
380 return rd;
856 Register rd,
859 ASSERT(rd.is_valid() && rs.is_valid() && rt.is_valid() && is_uint5(sa));
861 | (rd.code() << kRdShift) | (sa << kSaShift) | func;
1161 void Assembler::jalr(Register rs, Register rd) {
1164 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR);
1199 void Assembler::addu(Register rd, Register rs, Register rt) {
1200 GenInstrRegister(SPECIAL, rs, rt, rd, 0, ADDU);
1204 void Assembler::addiu(Register rd, Register rs, int32_t j) {
1205 GenInstrImmediate(ADDIU, rs, rd, j);
1209 void Assembler::subu(Register rd, Register rs, Register rt) {
1210 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SUBU);
1214 void Assembler::mul(Register rd, Register rs, Register rt) {
1215 GenInstrRegister(SPECIAL2, rs, rt, rd, 0, MUL);
1241 void Assembler::and_(Register rd, Register rs, Register rt) {
1242 GenInstrRegister(SPECIAL, rs, rt, rd, 0, AND);
1252 void Assembler::or_(Register rd, Register rs, Register rt) {
1253 GenInstrRegister(SPECIAL, rs, rt, rd, 0, OR);
1263 void Assembler::xor_(Register rd, Register rs, Register rt) {
1264 GenInstrRegister(SPECIAL, rs, rt, rd, 0, XOR);
1274 void Assembler::nor(Register rd, Register rs, Register rt) {
1275 GenInstrRegister(SPECIAL, rs, rt, rd, 0, NOR);
1280 void Assembler::sll(Register rd,
1288 ASSERT(coming_from_nop || !(rd.is(zero_reg) && rt.is(zero_reg)));
1289 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SLL);
1293 void Assembler::sllv(Register rd, Register rt, Register rs) {
1294 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLLV);
1298 void Assembler::srl(Register rd, Register rt, uint16_t sa) {
1299 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SRL);
1303 void Assembler::srlv(Register rd, Register rt, Register rs) {
1304 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRLV);
1308 void Assembler::sra(Register rd, Register rt, uint16_t sa) {
1309 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SRA);
1313 void Assembler::srav(Register rd, Register rt, Register rs) {
1314 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRAV);
1318 void Assembler::rotr(Register rd, Register rt, uint16_t sa) {
1320 ASSERT(rd.is_valid() && rt.is_valid() && is_uint5(sa));
1323 | (rd.code() << kRdShift) | (sa << kSaShift) | SRL;
1328 void Assembler::rotrv(Register rd, Register rt, Register rs) {
1330 ASSERT(rd.is_valid() && rt.is_valid() && rs.is_valid() );
1333 | (rd.code() << kRdShift) | (1 << kSaShift) | SRLV;
1349 void Assembler::lb(Register rd, const MemOperand& rs) {
1351 GenInstrImmediate(LB, rs.rm(), rd, rs.offset_);
1354 GenInstrImmediate(LB, at, rd, 0); // Equiv to lb(rd, MemOperand(at, 0));
1359 void Assembler::lbu(Register rd, const MemOperand& rs) {
1361 GenInstrImmediate(LBU, rs.rm(), rd, rs.offset_);
1364 GenInstrImmediate(LBU, at, rd, 0); // Equiv to lbu(rd, MemOperand(at, 0));
1369 void Assembler::lh(Register rd, const MemOperand& rs) {
1371 GenInstrImmediate(LH, rs.rm(), rd, rs.offset_);
1374 GenInstrImmediate(LH, at, rd, 0); // Equiv to lh(rd, MemOperand(at, 0));
1379 void Assembler::lhu(Register rd, const MemOperand& rs) {
1381 GenInstrImmediate(LHU, rs.rm(), rd, rs.offset_);
1384 GenInstrImmediate(LHU, at, rd, 0); // Equiv to lhu(rd, MemOperand(at, 0));
1389 void Assembler::lw(Register rd, const MemOperand& rs) {
1391 GenInstrImmediate(LW, rs.rm(), rd, rs.offset_);
1394 GenInstrImmediate(LW, at, rd, 0); // Equiv to lw(rd, MemOperand(at, 0));
1399 void Assembler::lwl(Register rd, const MemOperand& rs) {
1400 GenInstrImmediate(LWL, rs.rm(), rd, rs.offset_);
1404 void Assembler::lwr(Register rd, const MemOperand& rs) {
1405 GenInstrImmediate(LWR, rs.rm(), rd, rs.offset_);
1409 void Assembler::sb(Register rd, const MemOperand& rs) {
1411 GenInstrImmediate(SB, rs.rm(), rd, rs.offset_);
1414 GenInstrImmediate(SB, at, rd, 0); // Equiv to sb(rd, MemOperand(at, 0));
1419 void Assembler::sh(Register rd, const MemOperand& rs) {
1421 GenInstrImmediate(SH, rs.rm(), rd, rs.offset_);
1424 GenInstrImmediate(SH, at, rd, 0); // Equiv to sh(rd, MemOperand(at, 0));
1429 void Assembler::sw(Register rd, const MemOperand& rs) {
1431 GenInstrImmediate(SW, rs.rm(), rd, rs.offset_);
1434 GenInstrImmediate(SW, at, rd, 0); // Equiv to sw(rd, MemOperand(at, 0));
1439 void Assembler::swl(Register rd, const MemOperand& rs) {
1440 GenInstrImmediate(SWL, rs.rm(), rd, rs.offset_);
1444 void Assembler::swr(Register rd, const MemOperand& rs) {
1445 GenInstrImmediate(SWR, rs.rm(), rd, rs.offset_);
1449 void Assembler::lui(Register rd, int32_t j) {
1451 GenInstrImmediate(LUI, zero_reg, rd, j);
1540 void Assembler::mfhi(Register rd) {
1541 GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFHI);
1545 void Assembler::mflo(Register rd) {
1546 GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFLO);
1551 void Assembler::slt(Register rd, Register rs, Register rt) {
1552 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLT);
1556 void Assembler::sltu(Register rd, Register rs, Register rt) {
1557 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLTU);
1572 void Assembler::movz(Register rd, Register rs, Register rt) {
1573 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVZ);
1577 void Assembler::movn(Register rd, Register rs, Register rt) {
1578 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVN);
1582 void Assembler::movt(Register rd, Register rs, uint16_t cc) {
1585 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI);
1589 void Assembler::movf(Register rd, Register rs, uint16_t cc) {
1592 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI);
1597 void Assembler::clz(Register rd, Register rs) {
1598 // Clz instr requires same GPR number in 'rd' and 'rt' fields.
1599 GenInstrRegister(SPECIAL2, rs, rd, rd, 0, CLZ);
