Lines Matching full:instruction
78 void Stop(Instruction* instr);
99 bool SetBreakpoint(Instruction* breakpc);
100 bool DeleteBreakpoint(Instruction* breakpc);
125 void MipsDebugger::Stop(Instruction* instr) {
144 // Overwrite the instruction and address with nops.
148 sim_->set_pc(sim_->get_pc() + 2 * Instruction::kInstructionSize);
154 #define UNSUPPORTED() printf("Unsupported instruction.\n");
159 void MipsDebugger::Stop(Instruction* instr) {
164 Instruction::kInstrSize);
170 sim_->set_pc(sim_->get_pc() + 2 * Instruction::kInstrSize);
240 bool MipsDebugger::SetBreakpoint(Instruction* breakpc) {
249 // Not setting the breakpoint instruction in the code itself. It will be set
255 bool MipsDebugger::DeleteBreakpoint(Instruction* breakpc) {
405 Instruction* instr = reinterpret_cast<Instruction*>(sim_->get_pc());
409 reinterpret_cast<Instruction*>(sim_->get_pc()));
413 sim_->set_pc(sim_->get_pc() + Instruction::kInstrSize);
416 // Execute the one instruction we broke at with breakpoints disabled.
417 sim_->InstructionDecode(reinterpret_cast<Instruction*>(sim_->get_pc()));
555 end = cur + (10 * Instruction::kInstrSize);
564 end = cur + (10 * Instruction::kInstrSize);
572 end = cur + (value * Instruction::kInstrSize);
580 end = cur + (value2 * Instruction::kInstrSize);
588 cur += Instruction::kInstrSize;
598 if (!SetBreakpoint(reinterpret_cast<Instruction*>(value))) {
616 2 * Instruction::kInstrSize;
617 Instruction* stop_instr = reinterpret_cast<Instruction*>(stop_pc);
618 Instruction* msg_address =
619 reinterpret_cast<Instruction*>(stop_pc +
620 Instruction::kInstrSize);
689 end = cur + (10 * Instruction::kInstrSize);
695 end = cur + (10 * Instruction::kInstrSize);
702 end = cur + (value2 * Instruction::kInstrSize);
710 cur += Instruction::kInstrSize;
716 PrintF(" step one instruction (alias 'si')\n");
757 PrintF(" ignore the stop instruction at the current location\n");
854 Instruction* instr) {
867 Instruction::kInstrSize) == 0);
931 // reference to a swi (software-interrupt) instruction that is handled by
933 // offset from the swi instruction so the simulator knows what to call.
946 Instruction::kInstrSize);
967 static Redirection* FromSwiInstruction(Instruction* swi_instruction) {
1044 return registers_[reg] + ((reg == pc) ? Instruction::kPCReadOffset : 0);
1226 int Simulator::ReadW(int32_t addr, Instruction* instr) {
1247 void Simulator::WriteW(int32_t addr, int value, Instruction* instr) {
1268 double Simulator::ReadD(int32_t addr, Instruction* instr) {
1281 void Simulator::WriteD(int32_t addr, double value, Instruction* instr) {
1294 uint16_t Simulator::ReadHU(int32_t addr, Instruction* instr) {
1307 int16_t Simulator::ReadH(int32_t addr, Instruction* instr) {
1320 void Simulator::WriteH(int32_t addr, uint16_t value, Instruction* instr) {
1333 void Simulator::WriteH(int32_t addr, int16_t value, Instruction* instr) {
1379 void Simulator::Format(Instruction* instr, const char* format) {
1380 PrintF("Simulator found unsupported instruction:\n 0x%08x: %s\n",
1413 void Simulator::SoftwareInterrupt(Instruction* instr) {
1415 // the break_ instruction, or several variants of traps. All
1592 void Simulator::HandleStop(uint32_t code, Instruction* instr) {
1599 set_pc(get_pc() + 2 * Instruction::kInstrSize);
1604 bool Simulator::IsStopInstruction(Instruction* instr) {
1678 // Handle execution based on instruction types.
1680 void Simulator::ConfigureTypeRegister(Instruction* instr,
1690 // Instruction fields.
1750 // bits instruction. RS field is always equal to 0.
1754 // is special case of SRL instruction, added in MIPS32 Release 2.
1768 // bits instruction. SA field is always equal to 0.
1772 // This is special case od SRLV instruction, added in MIPS32
1886 case INS: { // Mips32r2 instruction.
1896 case EXT: { // Mips32r2 instruction.
1916 void Simulator::DecodeTypeRegister(Instruction* instr) {
1917 // Instruction fields.
1947 // Set up the variables if needed before executing the instruction.
2116 case TRUNC_L_D: { // Mips32r2 instruction.
2123 case ROUND_L_D: { // Mips32r2 instruction.
2130 case FLOOR_L_D: // Mips32r2 instruction.
2135 case CEIL_L_D: // Mips32r2 instruction.
2163 case CVT_D_L: // Mips32r2 instruction.
2186 Instruction* branch_delay_instr = reinterpret_cast<Instruction*>(
2187 current_pc+Instruction::kInstrSize);
2194 Instruction* branch_delay_instr = reinterpret_cast<Instruction*>(
2195 current_pc+Instruction::kInstrSize);
2197 set_register(31, current_pc + 2 * Instruction::kInstrSize);
2295 void Simulator::DecodeTypeImmediate(Instruction* instr) {
2296 // Instruction fields.
2344 next_pc = current_pc + (imm16 << 2) + Instruction::kInstrSize;
2380 next_pc = current_pc + (imm16 << 2) + Instruction::kInstrSize;
2538 next_pc = current_pc + (imm16 << 2) + Instruction::kInstrSize;
2540 set_register(31, current_pc + 2* Instruction::kInstrSize);
2543 next_pc = current_pc + 2 * Instruction::kInstrSize;
2605 Instruction* branch_delay_instr =
2606 reinterpret_cast<Instruction*>(current_pc+Instruction::kInstrSize);
2618 void Simulator::DecodeTypeJump(Instruction* instr) {
2629 Instruction* branch_delay_instr =
2630 reinterpret_cast<Instruction*>(current_pc + Instruction::kInstrSize);
2636 set_register(31, current_pc + 2 * Instruction::kInstrSize);
2643 // Executes the current instruction.
2644 void Simulator::InstructionDecode(Instruction* instr) {
2660 case Instruction::kRegisterType:
2663 case Instruction::kImmediateType:
2666 case Instruction::kJumpType:
2674 Instruction::kInstrSize);
2686 // should be stopping at a particular executed instruction.
2688 Instruction* instr = reinterpret_cast<Instruction*>(program_counter);
2697 Instruction* instr = reinterpret_cast<Instruction*>(program_counter);
