Lines Matching full:insns
50 taking into account the number of insns guarded by an IT.
147 the result of insns we wouldn't normally consider branchy. */
1050 /*--- Helpers for flag handling and conditional insns ---*/
2137 Most but not all ARM and Thumb integer insns use this encoding.
2230 Most but not all ARM and Thumb integer insns use this encoding.
2288 For ARM insns only; not for Thumb.
2623 Also produce the t/e chars for the 2nd, 3rd, 4th insns, for
8264 code, this must always be IRTemp_INVALID because NEON insns are
11562 /* --------------------- dp insns (D) --------------------- */
12024 /* --------------------- dp insns (F) --------------------- */
12412 assert that we aren't accepting, in this fn, insns that actually
12513 /* ------------------- v7 barrier insns ------------------- */
12620 /* At least this is simple on ARM: insns are all 4 bytes long, and
14890 /* Insns could be 2 or 4 bytes long. Just get the first 16 bits at
14972 the instruction word, first for 16-bit insns, then for 32-bit
14973 insns. */
14993 FIXME: do better. Take into account the number of insns covered
14994 by any IT insns we find, to rule out cases where an IT clearly
15036 the number of insns covered by it (1 .. 4) and check to
15046 /* # guarded insns */
15175 /* Same strategy as for ARM insns: generate a condition
16577 /* Change result defaults to suit 32-bit insns. */
18698 /* -------------- v7 barrier insns -------------- */
18952 /* Helper table for figuring out how many insns an IT insn
