Lines Matching refs:INSN
134 insn is Thumb (True) or ARM (False). */
185 /*--- arm insn stream. ---*/
488 happened, because the first insn's write to the block is
527 r15, record info so at the end of this insn's translation, a branch
1407 /* ditto, but jump over a 16-bit thumb insn */
1425 /* ditto, but jump over a 32-bit thumb insn */
5238 # define INSN(_bMax,_bMin) SLICE_UInt(theInstr, (_bMax), (_bMin))
5239 UInt U = INSN(24,24);
5243 UInt size = INSN(21,20);
5245 UInt Q = INSN(24,24);
5247 if (INSN(27,25) != 1 || INSN(23,23) != 1
5248 || INSN(6,6) != 1 || INSN(4,4) != 0)
5252 if ((INSN(11,8) & BITS4(1,0,1,0)) == BITS4(0,0,0,0)) {
5310 if (INSN(8,8)) {
5343 op2 = INSN(10,10) ? sub : add;
5351 DIP("vml%c.%c%u %c%u, %c%u, d%u[%u]\n", INSN(10,10) ? 's' : 'a',
5352 INSN(8,8) ? 'f' : 'i', 8 << size,
5358 if ((INSN(11,8) & BITS4(1,0,1,1)) == BITS4(0,0,1,0)) {
5405 op2 = INSN(10,10) ? sub : add;
5409 INSN(10,10) ? 's' : 'a', U ? 'u' : 's',
5415 if ((INSN(11,8) & BITS4(1,0,1,1)) == BITS4(0,0,1,1) && !U) {
5418 UInt P = INSN(10,10);
5491 if ((INSN
5549 if (INSN(8,8)) {
5581 DIP("vmul.%c%u %c%u, %c%u, d%u[%u]\n", INSN(8,8) ? 'f' : 'i',
5588 if (INSN(11,8) == BITS4(1,0,1,0)) {
5632 if (INSN(11,8) == BITS4(1,0,1,1) && !U) {
5697 if (INSN(11,8) == BITS4(1,1,0,0)) {
5797 if (INSN(11,8) == BITS4(1,1,0,1)) {
5897 # undef INSN
7951 # define INSN(_bMax,_bMin) SLICE_UInt(theInstr, (_bMax), (_bMin))
7952 UInt bA = INSN(23,23);
7953 UInt fB = INSN(11,8);
7954 UInt bL = INSN(21,21);
7955 UInt rD = (INSN(22,22) << 4) | INSN(15,12);
7956 UInt rN = INSN(19,16);
7957 UInt rM = INSN(3,0);
7970 if (INSN(20,20) != 0)
7993 case 0: i = INSN(7,5); inc = 1; break;
7994 case 1: i = INSN(7,6); inc = INSN(5,5) ? 2 : 1; break;
7995 case 2: i = INSN(7,7); inc = INSN(6,6) ? 2 : 1; break;
8031 inc = INSN(5,5) + 1;
8032 size = INSN(7,6);
8035 if (size == 3 && N == 3 && INSN(4,4) == 1)
8038 if (size == 0 && N == 0 && INSN(4,4) == 1)
8040 if (N == 2 && INSN(4,4) == 1)
8053 if (N == 0 && INSN(5,5))
8174 size = INSN(7,6);
8222 DIP("v%s%u.%u {", bL ? "ld" : "st", N + 1, 8 << INSN(7,6));
8243 # undef INSN
8263 or IRTemp_INVALID indicating the insn is always executed. In ARM
8277 # define INSN(_bMax,_bMin) SLICE_UInt(insn32, (_bMax), (_bMin))
8295 if (!isT && INSN(31,25) == BITS7(1,1,1,1,0,0,1)) {
8297 INSN(31,0), condT);
8299 if (isT && INSN(31,29) == BITS3(1,1,1)
8300 && INSN(27,24) == BITS4(1,1,1,1)) {
8302 UInt reformatted = INSN(23,0);
8303 reformatted |= (INSN(28,28) << 24); // U bit
8312 if (!isT && INSN(31,24) == BITS8(1,1,1,1,0,1,0,0)) {
8314 return dis_neon_load_or_store(INSN(31,0), isT, condT);
8316 if (isT && INSN(31,24) == BITS8(1,1,1,1,1,0,0,1)) {
8317 UInt reformatted = INSN(23,0);
8325 # undef INSN
8345 or IRTemp_INVALID indicating the insn is always executed.
10688 calling this, if the insn is to be conditional. Caller is
10885 the insn (yay!) and that's what the caller must supply, iow, imm28
10888 insn. The rules for the top 4 bits are:
10899 or IRTemp_INVALID indicating the insn is always executed.
10919 # define INSN(_bMax,_bMin) SLICE_UInt(insn28, (_bMax), (_bMin))
10921 vassert(INSN(31,28) == BITS4(0,0,0,0)); // caller's obligation
10954 if (BITS8(1,1,0,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,0,0,0,0,0))
10955 && INSN(11,8) == BITS4(1,0,1,1)) {
10961 UInt rN = INSN(19,16);
10962 UInt dD = (INSN(22,22) << 4) | INSN(15,12);
11007 /* make a new value for Rn, post-insn */
11091 if (BITS8(1,1,0,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,0,0,0,0,0))
11092 && INSN(11,8) == BITS4(1,0,1,1)) {
11098 UInt rN = INSN(19,16);
11099 UInt dD = (INSN(22,22) << 4) | INSN(15,12);
11144 /* make a new value for Rn, post-insn */
11208 if (BITS8(1,1,1,0,1,1,1,1) == INSN(27,20)
11209 && BITS4(1,0,1,0) == INSN(11,8)
11211 UInt rD = INSN(15,12);
11212 UInt reg = INSN(19,16);
11238 if (BITS8(1,1,1,0,1,1,1,0) == INSN(27,20)
11239 && BITS4(1,0,1,0) == INSN(11,8)
11241 UInt rD = INSN(15,12);
11242 UInt reg = INSN(19,16);
11255 UInt dM = INSN(3,0) | (INSN(5,5) << 4);
11256 UInt rD = INSN(15,12); /* lo32 */
11257 UInt rN = INSN(19,16); /* hi32 */
11275 UInt dM = INSN(3,0) | (INSN(5,5) << 4);
11276 UInt rD = INSN(15,12); /* lo32 */
11277 UInt rN = INSN(19,16); /* hi32 */
11301 UInt sD = (INSN(3,0) << 1) | INSN(5,5);
11302 UInt rN = INSN(15,12);
11303 UInt rM = INSN(19,16);
11322 UInt sD = (INSN(3,0) << 1) | INSN(5,5);
11323 UInt rN = INSN(15,12);
11324 UInt rM = INSN(19,16);
11346 UInt rD = (INSN(7,7) << 4) | INSN(19,16);
11347 UInt rT = INSN(15,12);
11348 UInt opc = (INSN(22,21) << 2) | INSN(6,5);
11393 UInt rN = (INSN(7,7) << 4) | INSN(19,16);
11394 UInt rT = INSN(15,12);
11395 UInt U = INSN(23,23);
11396 UInt opc = (INSN(22,21) << 2) | INSN(6,5);
11446 if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
11447 && BITS4(0,0,0,0) == INSN(7,4) && INSN(11,8) == BITS4(1,0,1,0)) {
11448 UInt rD = (INSN(15,12) << 1) | INSN(22,22);
11449 UInt imm8 = (INSN(19,16) << 4) | INSN(3,0);
11462 if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
11463 && BITS4(0,0,0,0) == INSN(7,4) && INSN(11,8) == BITS4(1,0,1,1)) {
11464 UInt rD = INSN(15,12) | (INSN(22,22) << 4);
11465 UInt imm8 = (INSN(19,16) << 4) | INSN(3,0);
11479 if (BITS8(1,1,1,0,1,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,0,1))
11480 && BITS4(1,0,1,1) == INSN(11,8) && INSN(6,6) == 0 && INSN(4,4) == 1) {
11481 UInt rD = (INSN(7,7) << 4) | INSN(19,16);
11482 UInt rT = INSN(15,12);
11483 UInt Q = INSN(21,21);
11484 UInt size = (INSN(22,22) << 1) | INSN(5,5);
11531 if (BITS8(1,1,0,1,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,0,0,1,0))
11532 && BITS4(1,0,1,1) == INSN(11,8)) {
11533 UInt dD = INSN(15,12) | (INSN(22,22) << 4);
11534 UInt rN = INSN(19,16);
11563 if (BITS8(1,1,1,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,0,0,0,0))
11564 && BITS4(1,0,1,1) == INSN(11,8)
11565 && BITS4(0,0,0,0) == (INSN(7,4) & BITS4(0,0,0,1))) {
11566 UInt dM = INSN(3,0) | (INSN(5,5) << 4); /* argR */
11567 UInt dD = INSN(15,12) | (INSN(22,22) << 4); /* dst/acc */
11568 UInt dN = INSN(19,16) | (INSN(7,7) << 4); /* argL */
11658 if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
11659 && BITS4(0,1,0,0) == (INSN(19,16) & BITS4(1,1,1,0))
11660 && BITS4(1,0,1,1) == INSN(11,8)
11661 && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) {
11664 UInt dD = INSN(15,12) | (INSN(22,22) << 4);
11665 UInt dM = INSN(3,0) | (INSN(5,5) << 4);
11666 if (bZ && INSN(3,0) != 0) {
11715 if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
11716 && BITS4(0,0,0,0) == (INSN(19,16) & BITS4(1,1,1,0))
11717 && BITS4(1,0,1,1) == INSN(11,8)
11718 && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) {
11719 UInt dD = INSN(15,12) | (INSN(22,22) << 4);
11720 UInt dM = INSN(3,0) | (INSN(5,5) << 4);
11757 if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
11758 && BITS4(1,0,0,0) == (INSN(19,16) & BITS4(1,1,1,1))
11759 && BITS4(1,0,1,1) == INSN(11,8)
11760 && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) {
11762 UInt fM = (INSN(3,0) << 1) | bM;
11763 UInt dD = INSN(15,12) | (INSN(22,22) << 4);
11782 if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
11783 && BITS4(1,1,0,0) == (INSN(19,16) & BITS4(1,1,1,0))
11784 && BITS4(1,0,1,1) == INSN(11,8)
11785 && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) {
11787 UInt fD = (INSN(15,12) << 1) | bD;
11788 UInt dM = INSN(3,0) | (INSN(5,5) << 4);
11839 if (BITS8(1,1,0,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,0,0,0,0,0))
11840 && INSN(11,8) == BITS4(1,0,1,0)) {
11847 UInt rN = INSN(19,16);
11848 UInt fD = (INSN(15,12) << 1) | bD;
11893 /* make a new value for Rn, post-insn */
11957 if (BITS8(1,1,1,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,1,1,0))
11958 && BITS4(1,0,1,0) == INSN(11,8)
11959 && BITS4(0,0,0,0) == INSN(3,0)
11960 && BITS4(0,0,0,1) == (INSN(7,4) & BITS4(0,1,1,1))) {
11961 UInt rD = INSN(15,12);
11963 UInt fN = (INSN(19,16) << 1) | b7;
11992 if (BITS8(1,1,0,1,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,0,0,1,0))
11993 && BITS4(1,0,1,0) == INSN(11,8)) {
11995 UInt fD = (INSN(15,12) << 1) | bD;
11996 UInt rN = INSN(19,16);
12025 if (BITS8(1,1,1,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,0,0,0,0))
12026 && BITS4(1,0,1,0) == (INSN(11,8) & BITS4(1,1,1,0))
12027 && BITS4(0,0,0,0) == (INSN(7,4) & BITS4(0,0,0,1))) {
12031 UInt fM = (INSN(3,0) << 1) | bM; /* argR */
12032 UInt fD = (INSN(15,12) << 1) | bD; /* dst/acc */
12033 UInt fN = (INSN(19,16) << 1) | bN; /* argL */
12122 if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
12123 && BITS4(0,1,0,0) == (INSN(19,16) & BITS4(1,1,1,0))
12124 && BITS4(1,0,1,0) == INSN(11,8)
12125 && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) {
12130 UInt fD = (INSN(15,12) << 1) | bD;
12131 UInt fM = (INSN(3,0) << 1) | bM;
12132 if (bZ && (INSN(3,0) != 0 || (INSN(7,4) & 3) != 0)) {
12184 if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
12185 && BITS4(0,0,0,0) == (INSN(19,16) & BITS4(1,1,1,0))
12186 && BITS4(1,0,1,0) == INSN(11,8)
12187 && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) {
12190 UInt fD = (INSN(15,12) << 1) | bD;
12191 UInt fM = (INSN(3,0) << 1) | bM;
12233 if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
12234 && BITS4(1,0,0,0) == INSN(19,16)
12235 && BITS4(1,0,1,0) == (INSN(11,8) & BITS4(1,1,1,0))
12236 && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) {
12239 UInt fM = (INSN(3,0) << 1) | bM;
12240 UInt fD = (INSN(15,12) << 1) | bD;
12265 if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
12266 && BITS4(1,1,0,0) == (INSN(19,16) & BITS4(1,1,1,0))
12267 && BITS4(1,0,1,0) == INSN(11,8)
12268 && BITS4(0,1,0,0) == (INSN(7,4) & BITS4(0,1,0,1))) {
12271 UInt fD = (INSN(15,12) << 1) | bD;
12272 UInt fM = (INSN(3,0) << 1) | bM;
12302 if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
12303 && BITS4(0,1,1,1) == INSN(19,16)
12304 && BITS4(1,0,1,0) == INSN(11,8)
12305 && BITS4(1,1,0,0) == (INSN(7,4) & BITS4(1,1,0,1))) {
12306 UInt dD = INSN(15,12) | (INSN(22,22) << 4);
12308 UInt fM = (INSN(3,0) << 1) | bM;
12315 if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
12316 && BITS4(0,1,1,1) == INSN(19,16)
12317 && BITS4(1,0,1,1) == INSN(11,8)
12318 && BITS4(1,1,0,0) == (INSN(7,4) & BITS4(1,1,0,1))) {
12320 UInt fD = (INSN(15,12) << 1) | bD;
12321 UInt dM = INSN(3,0) | (INSN(5,5) << 4);
12342 if (BITS8(1,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
12343 && BITS4(1,0,1,0) == (INSN(19,16) & BITS4(1,0,1,0))
12344 && BITS3(1,0,1) == INSN(11,9)
12345 && BITS3(1,0,0) == (INSN(6,4) & BITS3(1,0,1))) {
12346 UInt bD = INSN(22,22);
12347 UInt bOP = INSN(18,18);
12348 UInt bU = INSN(16,16);
12349 UInt Vd = INSN(15,12);
12350 UInt bSF = INSN(8,8);
12351 UInt bSX = INSN(7,7);
12352 UInt bI = INSN(5,5);
12353 UInt imm4 = INSN(3,0);
12366 assign(rmode, mkU32(Irrm_NEAREST)); // rmode that this insn is defd to use
12411 /* Check that any accepted insn really is a CP10 or CP11 insn, iow,
12414 vassert(INSN(11,9) == BITS3(1,0,1)); // 11:8 = 1010 or 1011
12417 # undef INSN
12435 UInt insn )
12437 # define INSNinsn, (_bMax), (_bMin))
12438 # define INSN_COND SLICE_UInt(insn, 31, 28)
12446 if (BITS8(0,1,0,1, 0, 1,0,1) == (INSN(27,20) & BITS8(1,1,1,1,0,1,1,1))
12447 && BITS4(1,1,1,1) == INSN(15,12)) {
12448 UInt rN = INSN(19,16);
12449 UInt imm12 = INSN(11,0);
12450 UInt bU = INSN(23,23);
12455 if (BITS8(0,1,1,1, 0, 1,0,1) == (INSN(27,20) & BITS8(1,1,1,1,0,1,1,1))
12456 && BITS4(1,1,1,1) == INSN(15,12)
12457 && 0 == INSN(4,4)) {
12458 UInt rN = INSN(19,16);
12459 UInt rM = INSN(3,0);
12460 UInt imm5 = INSN(11,7);
12461 UInt sh2 = INSN(6,5);
12462 UInt bU = INSN(23,23);
12479 if (BITS8(0,1,0,0, 0, 1,0,1) == (INSN(27,20) & BITS8(1,1,1,1,0,1,1,1))
12480 && BITS4(1,1,1,1) == INSN(15,12)) {
12481 UInt rN = INSN(19,16);
12482 UInt imm12 = INSN(11,0);
12483 UInt bU = INSN(23,23);
12492 if (INSN(31,25) == BITS7(1,1,1,1,1,0,1)) {
12493 UInt bitH = INSN(24,24);
12494 Int uimm24 = INSN(23,0);
12496 /* Now this is a bit tricky. Since we're decoding an ARM insn,
12497 it is implies that CPSR.T == 0. Hence the current insn's
12514 switch (insn) {
12546 if (insn == 0xF57FF01F) {
12558 dres, insn, IRTemp_INVALID/*unconditional*/,
12569 # undef INSN
12592 // A macro to fish bits out of 'insn'.
12593 # define INSN(_bMax,_bMin) SLICE_UInt(insn, (_bMax), (_bMin))
12594 # define INSN_COND SLICE_UInt(insn, 31, 28)
12597 UInt insn;
12604 /* What insn variants are we supporting today? */
12614 /* Set default actions for post-insn handling of writes to r15, if
12623 insn = getUIntLittleEndianly( guest_instr );
12625 if (0) vex_printf("insn: 0x%x\n", insn);
12682 can print the insn following the Special-insn preamble. */
12683 insn = getUIntLittleEndianly(code+16);
12705 Bool ok = decode_NV_instruction(&dres, archinfo, insn);
12728 if (0 == (INSN(27,20) & BITS8(1,1,0,0,0,0,0,0))
12729 && !(INSN(25,25) == 0 && INSN(7,7) == 1 && INSN(4,4) == 1)) {
12732 UInt rD = (insn >> 12) & 0xF; /* 15:12 */
12733 UInt rN = (insn >> 16) & 0xF; /* 19:16 */
12734 UInt bitS = (insn >> 20) & 1; /* 20:20 */
12743 switch (INSN(24,21)) {
12763 switch (INSN(24,21)) {
12774 INSN(25,25), INSN(11,0),
12841 Bool isMVN = INSN(24,21) == BITS4(1,1,1,1);
12846 INSN(25,25), INSN(11,0),
12863 if (!isMVN && INSN(11,0) == 14) {
12882 Bool isCMN = INSN(24,21) == BITS4(1,0,1,1);
12890 INSN(25,25), INSN(11,0),
12908 Bool isTEQ = INSN(24,21) == BITS4(1,0,0,1);
12916 INSN(25,25), INSN(11,0),
12948 INSN(25,25), INSN(11,0),
12957 switch (INSN(24,21)) {
12990 switch (INSN(24,21)) {
13016 } /* if (0 == (INSN(27,20) & BITS8(1,1,0,0,0,0,0,0)) */
13038 if ((INSN(27,24) & BITS4(1,1,0,0)) != BITS4(0,1,0,0))
13043 /**/ if (INSN(27,24) == BITS4(0,1,0,1) && INSN(21,21) == 0) {
13046 else if (INSN(27,24) == BITS4(0,1,1,1) && INSN(21,21) == 0
13047 && INSN(4,4) == 0) {
13050 else if (INSN(27,24) == BITS4(0,1,0,1) && INSN(21,21) == 1) {
13053 else if (INSN(27,24) == BITS4(0,1,1,1) && INSN(21,21) == 1
13054 && INSN(4,4) == 0) {
13057 else if (INSN(27,24) == BITS4(0,1,0,0) && INSN(21,21) == 0) {
13060 else if (INSN(27,24) == BITS4(0,1,1,0) && INSN(21,21) == 0
13061 && INSN(4,4) == 0) {
13066 { UInt rN = (insn >> 16) & 0xF; /* 19:16 */
13067 UInt rD = (insn >> 12) & 0xF; /* 15:12 */
13068 UInt rM = (insn >> 0) & 0xF; /* 3:0 */
13069 UInt bU = (insn >> 23) & 1; /* 23 */
13070 UInt bB = (insn >> 22) & 1; /* 22 */
13071 UInt bL = (insn >> 20) & 1; /* 20 */
13072 UInt imm12 = (insn >> 0) & 0xFFF; /* 11:0 */
13073 UInt imm5 = (insn >> 7) & 0x1F; /* 11:7 */
13074 UInt sh2 = (insn >> 5) & 3; /* 6:5 */
13259 if ((INSN(27,24) & BITS4(1,1,1,0)) != BITS4(0,0,0,0))
13263 if ((INSN(7,4) & BITS4(1,0,0,1)) != BITS4(1,0,0,1))
13268 /**/ if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,21) == BITS2(1,0)) {
13271 else if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,21) == BITS2(0,0)) {
13274 else if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,21) == BITS2(1,1)) {
13277 else if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,21) == BITS2(0,1)) {
13280 else if (INSNINSN(22,21) == BITS2(1,0)) {
13283 else if (INSN(27,24) == BITS4(0,0,0,0) && INSN(22,21) == BITS2(0,0)) {
13288 { UInt rN = (insn >> 16) & 0xF; /* 19:16 */
13289 UInt rD = (insn >> 12) & 0xF; /* 15:12 */
13290 UInt rM = (insn >> 0) & 0xF; /* 3:0 */
13291 UInt bU = (insn >> 23) & 1; /* 23 U=1 offset+, U=0 offset- */
13292 UInt bL = (insn >> 20) & 1; /* 20 L=1 load, L=0 store */
13293 UInt bH = (insn >> 5) & 1; /* H=1 halfword, H=0 byte */
13294 UInt bS = (insn >> 6) & 1; /* S=1 signed, S=0 unsigned */
13295 UInt imm8 = ((insn >> 4) & 0xF0) | (insn & 0xF); /* 11:8, 3:0 */
13443 if (BITS8(1,0,0,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,0,0,1,0,0))) {
13450 UInt bINC = (insn >> 23) & 1;
13451 UInt bBEFORE = (insn >> 24) & 1;
13453 UInt bL = (insn >> 20) & 1; /* load=1, store=0 */
13454 UInt bW = (insn >> 21) & 1; /* Rn wback=1, no wback=0 */
13455 UInt rN = (insn >> 16) & 0xF;
13456 UInt regList = insn & 0xFFFF;
13497 if (BITS8(1,0,1,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,0,0,0,0,0))) {
13498 UInt link = (insn >> 24) & 1;
13499 UInt uimm24 = insn & ((1<<24)-1);
13536 we need to emit a side-exit to the insn following this
13558 continue disassembling at the insn immediately
13586 if (INSN(27,20) == BITS8(0,0,0,1,0,0,1,0)
13587 && INSN(19,12) == BITS8(1,1,1,1,1,1,1,1)
13588 && (INSN(11,4) == BITS8(1,1,1,1,0,0,1,1)
13589 || INSN(11,4) == BITS8(1,1,1,1,0,0,0,1))) {
13591 UInt link = (INSN(11,4) >> 1) & 1;
13592 UInt rM = INSN(3,0);
13628 if (INSN(27,20) == BITS8(0,0,0,1,0,1,1,0)
13629 && INSN(19,16) == BITS4(1,1,1,1)
13630 && INSN(11,4) == BITS8(1,1,1,1,0,0,0,1)) {
13631 UInt rD = INSN(15,12);
13632 UInt rM = INSN(3,0);
13649 if (BITS8(0,0,0,0,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,1,1,0))
13650 && INSN(15,12) == BITS4(0,0,0,0)
13651 && INSN(7,4) == BITS4(1,0,0,1)) {
13652 UInt bitS = (insn >> 20) & 1; /* 20:20 */
13653 UInt rD = INSN(19,16);
13654 UInt rS = INSN(11,8);
13655 UInt rM = INSN(3,0);
13691 if (BITS8(0,1,1,1,0,0,0,1) == INSN(27,20)
13692 && INSN(15,12) == BITS4(1,1,1,1)
13693 && INSN(7,4) == BITS4(0,0,0,1)) {
13694 UInt rD = INSN(19,16);
13695 UInt rM = INSN(11,8);
13696 UInt rN = INSN(3,0);
13713 if (BITS8(0,1,1,1,0,0,1,1) == INSN(27,20)
13714 && INSN(15,12) == BITS4(1,1,1,1)
13715 && INSN(7,4) == BITS4(0,0,0,1)) {
13716 UInt rD = INSN(19,16);
13717 UInt rM = INSN(11,8);
13718 UInt rN = INSN(3,0);
13735 if (BITS8(0,0,0,0,0,0,1,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,0))
13736 && INSN(7,4) == BITS4(1,0,0,1)) {
13737 UInt bitS = (insn >> 20) & 1; /* 20:20 */
13738 UInt isMLS = (insn >> 22) & 1; /* 22:22 */
13739 UInt rD = INSN(19,16);
13740 UInt rN = INSN(15,12);
13741 UInt rS = INSN(11,8);
13742 UInt rM = INSN(3,0);
13788 if (BITS8(0,0,0,0,1,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,0))
13789 && INSN(7,4) == BITS4(1,0,0,1)) {
13790 UInt bitS = (insn >> 20) & 1; /* 20:20 */
13791 UInt rDhi = INSN(19,16);
13792 UInt rDlo = INSN(15,12);
13793 UInt rS = INSN(11,8);
13794 UInt rM = INSN(3,0);
13795 UInt isS = (INSN(27,20) >> 2) & 1; /* 22:22 */
13837 if (BITS8(0,0,0,0,1,0,1,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,0))
13838 && INSN(7,4) == BITS4(1,0,0,1)) {
13839 UInt bitS = (insn >> 20) & 1; /* 20:20 */
13840 UInt rDhi = INSN(19,16);
13841 UInt rDlo = INSN(15,12);
13842 UInt rS = INSN(11,8);
13843 UInt rM = INSN(3,0);
13844 UInt isS = (INSN(27,20) >> 2) & 1; /* 22:22 */
13892 if (INSN(27,20) == BITS8(0,0,1,1,0,0,1,0)
13893 && INSN(17,12) == BITS6(0,0,1,1,1,1)) {
13894 UInt write_ge = INSN(18,18);
13895 UInt write_nzcvq = INSN(19,19);
13897 UInt imm = (INSN(11,0) >> 0) & 0xFF;
13898 UInt rot = 2 * ((INSN(11,0) >> 8) & 0xF);
13912 if (INSN(27,20) == BITS8(0,0,0,1,0,0,1,0)
13913 && INSN(17,12) == BITS6(0,0,1,1,1,1)
13914 && INSN(11,4) == BITS8(0,0,0,0,0,0,0,0)) {
13915 UInt rN = INSN(3,0);
13916 UInt write_ge = INSN(18,18);
13917 UInt write_nzcvq = INSN(19,19);
13930 if ((insn & 0x0FFF0FFF) == 0x010F0000) {
13931 UInt rD = INSN(15,12);
13942 if (BITS8(1,1,1,1,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,0,0,0,0))) {
13943 UInt imm24 = (insn >> 0) & 0xFFFFFF;
13962 if (BITS8(0,0,0,1,0,0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
13963 && BITS4(0,0,0,0) == INSN(11,8)
13964 && BITS4(1,0,0,1) == INSN(7,4)) {
13965 UInt rN = INSN(19,16);
13966 UInt rD = INSN(15,12);
13967 UInt rM = INSN(3,0);
13972 UInt isB = (insn >> 22) & 1;
14020 if (0x01900F9F == (insn & 0x0F900FFF)) {
14021 UInt rT = INSN(15,12);
14022 UInt rN = INSN(19,16);
14027 switch (INSN(22,21)) {
14074 if (0x01800F90 == (insn & 0x0F900FF0)) {
14075 UInt rT = INSN(3,0);
14076 UInt rN = INSN(19,16);
14077 UInt rD = INSN(15,12);
14082 switch (INSN(22,21)) {
14140 if (0x03000000 == (insn & 0x0FF00000)
14141 || 0x03400000 == (insn & 0x0FF00000)) /* pray for CSE */ {
14142 UInt rD = INSN(15,12);
14143 UInt imm16 = (insn & 0xFFF) | ((insn >> 4) & 0x0000F000);
14144 UInt isT = (insn >> 22) & 1;
14168 if (BITS8(0,1,1,0,1, 0,0,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,0,0))
14169 && BITS4(1,1,1,1) == INSN(19,16)
14170 && BITS4(0,1,1,1) == INSN(7,4)
14171 && BITS4(0,0, 0,0) == (INSN(11,8) & BITS4(0,0,1,1))) {
14172 UInt subopc = INSN(27,20) & BITS8(0,0,0,0,0, 1,1,1);
14174 Int rot = (INSN(11,8) >> 2) & 3;
14175 UInt rM = INSN(3,0);
14176 UInt rD = INSN(15,12);
14235 if (BITS8(0,1,1,1,1,1,0, 0) == (INSN(27,20) & BITS8(1,1,1,1,1,1,1,0))
14236 && BITS4(0, 0,0,1) == (INSN(7,4) & BITS4(0,1,1,1))) {
14237 UInt rD = INSN(15,12);
14238 UInt rN = INSN(3,0);
14239 UInt msb = (insn >> 16) & 0x1F; /* 20:16 */
14240 UInt lsb = (insn >> 7) & 0x1F; /* 11:7 */
14279 if (BITS8(0,1,1,1,1,0,1,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,0))
14280 && BITS4(0,1,0,1) == (INSN(7,4) & BITS4(0,1,1,1))) {
14281 UInt rD = INSN(15,12);
14282 UInt rN = INSN(3,0);
14283 UInt wm1 = (insn >> 16) & 0x1F; /* 20:16 */
14284 UInt lsb = (insn >> 7) & 0x1F; /* 11:7 */
14286 UInt isU = (insn >> 22) & 1; /* 22:22 */
14335 if ((INSN(27,24) & BITS4(1,1,1,0)) != BITS4(0,0,0,0))
14339 if ((INSN(7,4) & BITS4(1,1,0,1)) != BITS4(1,1,0,1))
14344 /**/ if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,20) == BITS3(1,0,0)) {
14347 else if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,20) == BITS3(0,0,0)) {
14350 else if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,20) == BITS3(1,1,0)) {
14353 else if (INSN(27,24) == BITS4(0,0,0,1) && INSN(22,20) == BITS3(0,1,0)) {
14356 else if (INSN(27,24) == BITS4(0,0,0,0) && INSN(22,20) == BITS3(1,0,0)) {
14359 else if (INSN(27,24) == BITS4(0,0,0,0) && INSN(22,20) == BITS3(0,0,0)) {
14364 { UInt rN = (insn >> 16) & 0xF; /* 19:16 */
14365 UInt rD = (insn >> 12) & 0xF; /* 15:12 */
14366 UInt rM = (insn >> 0) & 0xF; /* 3:0 */
14367 UInt bU = (insn >> 23) & 1; /* 23 U=1 offset+, U=0 offset- */
14368 UInt bS = (insn >> 5) & 1; /* S=1 store, S=0 load */
14369 UInt imm8 = ((insn >> 4) & 0xF0) | (insn & 0xF); /* 11:8, 3:0 */
14493 if (BITS8(0,1,1,0,1,0,1,0) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
14494 && BITS4(0,0,0,0) == (INSN(11,8) & BITS4(0,0,1,1))
14495 && BITS4(0,1,1,1) == INSN(7,4)) {
14496 UInt rN = INSN(19,16);
14497 UInt rD = INSN(15,12);
14498 UInt rM = INSN(3,0);
14499 UInt rot = (insn >> 10) & 3;
14500 UInt isU = INSN(22,22);
14523 if (BITS8(0,1,1,0,1,0,1,1) == (INSN(27,20) & BITS8(1,1,1,1,1,0,1,1))
14524 && BITS4(0,0,0,0) == (INSN(11,8) & BITS4(0,0,1,1))
14525 && BITS4(0,1,1,1) == INSN(7,4)) {
14526 UInt rN = INSN(19,16);
14527 UInt rD = INSN(15,12);
14528 UInt rM = INSN(3,0);
14529 UInt rot = (insn >> 10) & 3;
14530 UInt isU = INSN(22,22);
14554 if (INSN(27,16) == 0x6BF
14555 && (INSN(11,4) == 0xFB/*rev16*/ || INSN(11,4) == 0xF3/*rev*/)) {
14556 Bool isREV = INSN(11,4) == 0xF3;
14557 UInt rM = INSN(3,0);
14558 UInt rD = INSN(15,12);
14571 if (INSN(27,16) == 0x6FF && INSN(11,4) == 0xF3) {
14572 UInt rD = INSN(15,12);
14573 UInt rM = INSN(3,0);
14585 if (INSN(27,20) == BITS8(0,1,1,1,0,1,0,1)
14586 && INSN(15,12) == BITS4(1,1,1,1)
14587 && (INSN(7,4) & BITS4(1,1,0,1)) == BITS4(0,0,0,1)) {
14588 UInt bitR = INSN(5,5);
14589 UInt rD = INSN(19,16);
14590 UInt rM = INSN(11,8);
14591 UInt rN = INSN(3,0);
14606 if (INSN(27,20) == BITS8(0,1,1,1,0,1,0,1)
14607 && INSN(15,12) != BITS4(1,1,1,1)
14608 && (INSN(7,4) & BITS4(1,1,0,1)) == BITS4(0,0,0,1)) {
14609 UInt bitR = INSN(5,5);
14610 UInt rD = INSN(19,16);
14611 UInt rA = INSN(15,12);
14612 UInt rM = INSN(11,8);
14613 UInt rN = INSN(3,0);
14630 if (0x0320F000 == (insn & 0x0FFFFFFF)) {
14646 if (0x0E1D0F70 == (insn & 0x0FFF0FFF)) {
14647 UInt rD = INSN(15,12);
14664 if (0xEE070FBA == (insn & 0xFFFF0FFF)) {
14665 UInt rT = INSN(15,12);
14676 switch (insn) {
14690 DIP("mcr 15, 0, r0, c7, c5, 4 (insn synch barrier)\n");
14702 &dres, INSN(27,0), condT, INSN_COND,
14721 &dres, INSN(27,0), condT, INSN_COND,
14738 "0x%x\n", insn);
14743 (Int)INSN(27,20), (UInt)INSN(27,20),
14744 (Int)INSN(4,4),
14745 (Int)INSN(3,0), (UInt)INSN(3,0) );
14747 /* Tell the dispatcher that this insn cannot be decoded, and so has
14750 insn, but nevertheless be paranoid and update it again right
14769 insn. That's reasonable, in the sense that the ARM insn set
14801 /* This seems crazy, but we're required to finish the insn with
14827 # undef INSN
14859 16-bit insn decoder, so as to stop it mistakenly being used
14864 UShort insn0; /* first 16 bits of the insn */
14865 UShort insn1; /* second 16 bits of the insn */
14874 /* What insn variants are we supporting today? */
14884 /* Set default actions for post-insn handling of writes to r15, if
14901 if (0) vex_printf("insn: 0x%x\n", insn0);
14960 can print the insn following the Special-insn preamble. */
14998 vs 32-bit insn length):
15022 insn. So, have a look at them. */
15023 guaranteedUnconditional = True; /* assume no 'it' insn found,
15045 /* might be an 'it' insn. */
15061 /* Generate the guarding condition for this insn, by examining
15067 decode_success handle this, but in cases where the insn contains
15251 insn, taking into account the guarding condition.
15665 // FIXME: what if we have to back up and restart this insn?
15698 /* jump over insn if not selected */
15748 /* jump over insn if not selected */
15804 /* Looks like the nearest insn we can branch to is the one after
15843 sequence, (1) jump over the insn if it is gated false, and
15897 sequence, (1) jump over the insn if it is gated false, and
16501 // and skip this insn if not selected; being cleverer is too
16609 // and skip this insn if not selected; being cleverer is too
16626 valid ARM insn address */
17787 "word-align(address of current insn + 4)". */
18013 /* If in an IT block, must be the last insn. */
18911 /* Tell the dispatcher that this insn cannot be decoded, and so has
18914 insn, but nevertheless be paranoid and update it again right
18952 /* Helper table for figuring out how many insns an IT insn
18986 case, since that isn't an IT insn at all. But for all the other
