Lines Matching refs:rT
11344 // VMOV rD[x], rT (ARM core register to scalar)
11347 UInt rT = INSN(15,12);
11350 if (rT == 15 || (isT && rT == 13)) {
11359 isT ? getIRegT(rT) : getIRegA(rT))),
11361 DIP("vmov%s.8 d%u[%u], r%u\n", nCC(conq), rD, index, rT);
11370 isT ? getIRegT(rT) : getIRegA(rT))),
11372 DIP("vmov%s.16 d%u[%u], r%u\n", nCC(conq), rD, index, rT);
11380 isT ? getIRegT(rT) : getIRegA(rT)),
11382 DIP("vmov%s.32 d%u[%u], r%u\n", nCC(conq), rD, index, rT);
11391 // VMOV rT, rD[x]
11394 UInt rT = INSN(15,12);
11398 if (rT == 15 || (isT && rT == 13)) {
11408 putIRegT(rT, e, condT);
11410 putIRegA(rT, e, condT, Ijk_Boring);
11412 rT, rN, index);
11422 putIRegT(rT, e, condT);
11424 putIRegA(rT, e, condT, Ijk_Boring);
11426 rT, rN, index);
11433 putIRegT(rT, e, condT);
11435 putIRegA(rT, e, condT, Ijk_Boring);
11436 DIP("vmov%s.32 r%u, d%u[%u]\n", nCC(conq), rT, rN, index);
11477 // VDUP dD, rT
11478 // VDUP qD, rT
11482 UInt rT = INSN(15,12);
11485 if (rT == 15 || (isT && rT == 13) || size == 3 || (Q && (rD & 1))) {
11488 IRExpr* e = isT ? getIRegT(rT) : getIRegA(rT);
11506 DIP("vdup.%u q%u, r%u\n", 32 / (1<<size), rD, rT);
11523 DIP("vdup.%u d%u, r%u\n", 32 / (1<<size), rD, rT);
14021 UInt rT = INSN(15,12);
14035 if (rT == 15 || rN == 15)
14039 if ((rT & 1) == 1 || rT == 14 || rN == 15)
14056 putIRegA(rT+0, unop(Iop_64to32, mkexpr(res)),
14058 putIRegA(rT+1, unop(Iop_64HIto32, mkexpr(res)),
14061 nm, nCC(INSN_COND), rT+0, rT+1, rN);
14063 putIRegA(rT, widen == Iop_INVALID
14066 DIP("ldrex%s%s r%u, [r%u]\n", nm, nCC(INSN_COND), rT, rN);
14075 UInt rT = INSN(3,0);
14090 if (rD == 15 || rN == 15 || rT == 15
14091 || rD == rN || rD == rT)
14095 if (rD == 15 || (rT & 1) == 1 || rT == 14 || rN == 15
14096 || rD == rN || rD == rT || rD == rT+1)
14111 ? binop(Iop_32HLto64, getIRegA(rT+1), getIRegA(rT+0))
14113 ? getIRegA(rT)
14114 : unop(narrow, getIRegA(rT)));
14129 nm, nCC(INSN_COND), rD, rT, rT+1, rN);
14132 nm, nCC(INSN_COND), rD, rT, rN);
14663 /* v6 */ /* mcr 15, 0, rT, c7, c10, 5 */
14665 UInt rT = INSN(15,12);
14666 if (rT <= 14) {
14667 /* mcr 15, 0, rT, c7, c10, 5 (v6) equiv to DMB (v7). Data
14670 DIP("mcr 15, 0, r%u, c7, c10, 5 (data memory barrier)\n", rT);
17410 op Rt, [Rn, #-imm8] or
17411 op Rt, [Rn], #+/-imm8 or
17412 op Rt, [Rn, #+/-imm8]!
17446 UInt rT = INSN1(15,12);
17460 if (bW == 1 && rN == rT)
17463 if (isBadRegT(rT))
17467 if (isST && rT == 15)
17469 if (!isST && rT == 15)
17506 assign(oldRt, getIRegT(rT));
17510 vassert(rN != rT); // assured by validity check above
17554 vassert(rT == 15);
17555 llPutIReg(rT, mkexpr(newRt));
17557 putIRegT(rT, mkexpr(newRt), IRTemp_INVALID);
17562 vassert(rN != rT); // assured by validity check above
17577 nm, rT, rN, bU ? '+' : '-', imm8);
17581 nm, rT, rN, bU ? '+' : '-', imm8);
17586 nm, rT, rN, bU ? '+' : '-', imm8);
17595 op Rt, [Rn, Rm, LSL #imm8]
17631 UInt rT = INSN1(15,12);
17638 if (rN == 15 || isBadRegT(rT) || isBadRegT(rM))
17644 if (isST && rT == 15)
17646 /* If it is a load and rT is 15, that's only allowable if we
17649 if (!isST && rT == 15)
17670 assign(oldRt, getIRegT(rT));
17710 vassert(rT == 15);
17711 llPutIReg(rT, mkexpr(newRt));
17713 putIRegT(rT, mkexpr(newRt), IRTemp_INVALID);
17725 nm, rT, rN, rM, imm2);
17733 op Rt, [Rn, +#imm12]
17767 UInt rT = INSN1(15,12);
17774 if (rN == 15 || isBadRegT(rT))
17779 if (rN == 15 || rT == 15)
17782 /* For a 32-bit load, rT == 15 is only allowable if we not
17788 if (rT == 15)
17816 assign(oldRt, getIRegT(rT));
17850 putIRegT(rT, mkexpr(newRt), IRTemp_INVALID);
17860 DIP("%s.w r%u, [r%u, +#%u]\n", nm, rT, rN, imm12);
17868 ldrd/strd Rt, Rt2, [Rn, #-imm8] or
17869 ldrd/strd Rt, Rt2, [Rn], #+/-imm8 or
17870 ldrd/strd Rt, Rt2, [Rn, #+/-imm8]!
17878 UInt rT = INSN1(15,12);
17884 if (bW == 1 && (rN == rT || rN == rT2)) valid = False;
17885 if (isBadRegT(rT) || isBadRegT(rT2)) valid = False;
17887 if (bL == 1 && rT == rT2) valid = False;
17907 assign(oldRt, getIRegT(rT));
17922 putIRegT(rT, mkexpr(newRt), IRTemp_INVALID);
17934 nm, rT, rT2, rN, bU ? '+' : '-', imm8 << 2);
17938 nm, rT, rT2, rN, bU ? '+' : '-', imm8 << 2);
17943 nm, rT, rT2, rN, bU ? '+' : '-', imm8 << 2);
18550 UInt rT = INSN1(15,12);
18552 if (!isBadRegT(rT) && rN != 15) {
18562 putIRegT(rT, mkexpr(res), IRTemp_INVALID);
18563 DIP("ldrex r%u, [r%u, #+%u]\n", rT, rN, imm8 * 4);
18572 UInt rT = INSN1(15,12);
18574 if (!isBadRegT(rT) && rN != 15) {
18582 putIRegT(rT, unop(isH ? Iop_16Uto32 : Iop_8Uto32, mkexpr(res)),
18584 DIP("ldrex%c r%u, [r%u]\n", isH ? 'h' : 'b', rT, rN);
18592 UInt rT = INSN1(15,12);
18594 if (!isBadRegT(rT) && !isBadRegT(rT2) && rT != rT2 && rN != 15) {
18604 putIRegT(rT, unop(Iop_64to32, mkexpr(res)), IRTemp_INVALID);
18606 DIP("ldrexd r%u, r%u, [r%u]\n", rT, rT2, rN);
18614 UInt rT = INSN1(15,12);
18617 if (!isBadRegT(rD) && !isBadRegT(rT) && rN != 15
18618 && rD != rN && rD != rT) {
18628 getIRegT(rT)) );
18635 DIP("strex r%u, r%u, [r%u, #+%u]\n", rD, rT, rN, imm8 * 4);
18644 UInt rT = INSN1(15,12);
18647 if (!isBadRegT(rD) && !isBadRegT(rT) && rN != 15
18648 && rD != rN && rD != rT) {
18657 getIRegT(rT))) );
18664 DIP("strex%c r%u, r%u, [r%u]\n", isH ? 'h' : 'b', rD, rT, rN);
18672 UInt rT = INSN1(15,12);
18675 if (!isBadRegT(rD) && !isBadRegT(rT) && !isBadRegT(rT2)
18676 && rN != 15 && rD != rN && rD != rT && rD != rT) {
18685 assign(data, binop(Iop_32HLto64, getIRegT(rT2), getIRegT(rT)));
18694 DIP("strexd r%u, r%u, r%u, [r%u]\n", rD, rT, rT2, rN);
