Lines Matching refs:addInstr
176 static void addInstr ( ISelEnv* env, AMD64Instr* instr )
323 addInstr(env,
331 addInstr(env,
343 addInstr( env, AMD64Instr_Push(AMD64RMI_Imm( (UInt)uimm64 )) );
346 addInstr( env, AMD64Instr_Imm64(uimm64, tmp) );
347 addInstr( env, AMD64Instr_Push(AMD64RMI_Reg(tmp)) );
505 addInstr (that is, commit to) any instructions until we're
530 addInstr(env, fastinstrs[i]);
551 addInstr(env, mk_iMOVsd_RR( hregAMD64_RBP(), tmpregs[argreg]));
581 addInstr( env, mk_iMOVsd_RR( tmpregs[i], argregs[i] ) );
587 addInstr(env, AMD64Instr_Call(
624 addInstr(env, mk_iMOVsd_RR(roff, tmp));
629 addInstr(env,
632 addInstr(env,
650 addInstr(env, AMD64Instr_Push(AMD64RMI_Imm(DEFAULT_MXCSR)));
651 addInstr(env, AMD64Instr_LdMXCSR(zero_rsp));
664 addInstr(env, AMD64Instr_Alu64M(
666 addInstr(env, AMD64Instr_A87LdCW(m8_rsp));
693 addInstr(env, AMD64Instr_Alu64R(Aalu_MOV, AMD64RMI_Imm(3), reg));
694 addInstr(env, AMD64Instr_Alu64R(Aalu_AND,
696 addInstr(env, AMD64Instr_Sh64(Ash_SHL, 13, reg));
697 addInstr(env, AMD64Instr_Alu64R(
699 addInstr(env, AMD64Instr_Push(AMD64RMI_Reg(reg)));
700 addInstr(env, AMD64Instr_LdMXCSR(zero_rsp));
724 addInstr(env, mk_iMOVsd_RR(rrm, rrm2));
725 addInstr(env, AMD64Instr_Alu64R(Aalu_AND, AMD64RMI_Imm(3), rrm2));
726 addInstr(env, AMD64Instr_Sh64(Ash_SHL, 10, rrm2));
727 addInstr(env, AMD64Instr_Alu64R(Aalu_OR,
729 addInstr(env, AMD64Instr_Alu64M(Aalu_MOV,
731 addInstr(env, AMD64Instr_A87LdCW(m8_rsp));
740 addInstr(env, AMD64Instr_SseReRg(Asse_XOR, dst, dst));
749 addInstr(env, AMD64Instr_SseReRg(Asse_CMPEQ32, dst, dst));
760 addInstr(env, AMD64Instr_SseReRg(Asse_XOR, src, dst));
845 addInstr(env, AMD64Instr_Alu64R(Aalu_MOV,
850 addInstr(env, AMD64Instr_LoadEX(4,False,amode,dst));
854 addInstr(env, AMD64Instr_LoadEX(2,False,amode,dst));
858 addInstr(env, AMD64Instr_LoadEX(1,False,amode,dst));
875 addInstr(env, mk_iMOVsd_RR(reg,dst));
876 addInstr(env, AMD64Instr_Unary64(Aun_NEG,dst));
903 addInstr(env, mk_iMOVsd_RR(reg,dst));
904 addInstr(env, AMD64Instr_Alu64R(aluOp, rmi, dst));
924 addInstr(env, mk_iMOVsd_RR(regL,dst));
933 addInstr(env, AMD64Instr_Alu64R(
937 addInstr(env, AMD64Instr_Alu64R(
941 addInstr(env, AMD64Instr_MovxLQ(False, dst, dst));
944 addInstr(env, AMD64Instr_Sh64(Ash_SHL, 56, dst));
945 addInstr(env, AMD64Instr_Sh64(Ash_SAR, 56, dst));
948 addInstr(env, AMD64Instr_Sh64(Ash_SHL, 48, dst));
949 addInstr(env, AMD64Instr_Sh64(Ash_SAR, 48, dst));
952 addInstr(env, AMD64Instr_MovxLQ(True, dst, dst));
969 addInstr(env, AMD64Instr_Sh64(shOp, nshift, dst));
973 addInstr(env, mk_iMOVsd_RR(regR,hregAMD64_RCX()));
974 addInstr(env, AMD64Instr_Sh64(shOp, 0/* %cl */, dst));
1126 addInstr(env, AMD64Instr_MovxLQ(False, argR, argR));
1127 addInstr(env, mk_iMOVsd_RR(argL, hregAMD64_RDI()) );
1128 addInstr(env, mk_iMOVsd_RR(argR, hregAMD64_RSI()) );
1129 addInstr(env, AMD64Instr_Call( Acc_ALWAYS, (ULong)fn, 2 ));
1130 addInstr(env, mk_iMOVsd_RR(hregAMD64_RAX(), dst));
1140 addInstr(env, mk_iMOVsd_RR(src1, dst));
1141 addInstr(env, AMD64Instr_Alu32R(Aalu_CMP, AMD64RMI_Reg(src2), dst));
1142 addInstr(env, AMD64Instr_CMov64(Acc_B, AMD64RM_Reg(src2), dst));
1159 addInstr(env, mk_iMOVsd_RR(left64, rdx));
1160 addInstr(env, mk_iMOVsd_RR(left64, rax));
1161 addInstr(env, AMD64Instr_Sh64(Ash_SHR, 32, rdx));
1162 addInstr(env, AMD64Instr_Div(syned, 4, rmRight));
1163 addInstr(env, AMD64Instr_MovxLQ(False, rdx, rdx));
1164 addInstr(env, AMD64Instr_MovxLQ(False, rax, rax));
1165 addInstr(env, AMD64Instr_Sh64(Ash_SHL, 32, rdx));
1166 addInstr(env, mk_iMOVsd_RR(rax, dst));
1167 addInstr(env, AMD64Instr_Alu64R(Aalu_OR, AMD64RMI_Reg(rdx), dst));
1176 addInstr(env, mk_iMOVsd_RR(hi32s, hi32));
1177 addInstr(env, mk_iMOVsd_RR(lo32s, lo32));
1178 addInstr(env, AMD64Instr_Sh64(Ash_SHL, 32, hi32));
1179 addInstr(env, AMD64Instr_MovxLQ(False, lo32, lo32));
1180 addInstr(env, AMD64Instr_Alu64R(
1190 addInstr(env, mk_iMOVsd_RR(hi16s, hi16));
1191 addInstr(env, mk_iMOVsd_RR(lo16s, lo16));
1192 addInstr(env, AMD64Instr_Sh64(Ash_SHL, 16, hi16));
1193 addInstr(env, AMD64Instr_Alu64R(
1195 addInstr(env, AMD64Instr_Alu64R(
1205 addInstr(env, mk_iMOVsd_RR(hi8s, hi8));
1206 addInstr(env, mk_iMOVsd_RR(lo8s, lo8));
1207 addInstr(env, AMD64Instr_Sh64(Ash_SHL, 8, hi8));
1208 addInstr(env, AMD64Instr_Alu64R(
1210 addInstr(env, AMD64Instr_Alu64R(
1237 addInstr(env, mk_iMOVsd_RR(a32s, a32));
1238 addInstr(env, mk_iMOVsd_RR(b32s, b32));
1239 addInstr(env, AMD64Instr_Sh64(Ash_SHL, shift, a32));
1240 addInstr(env, AMD64Instr_Sh64(Ash_SHL, shift, b32));
1241 addInstr(env, AMD64Instr_Sh64(shr_op, shift, a32));
1242 addInstr(env, AMD64Instr_Sh64(shr_op, shift, b32));
1243 addInstr(env, AMD64Instr_Alu64R(Aalu_MUL, AMD64RMI_Reg(a32), b32));
1251 addInstr(env, AMD64Instr_SseUComIS(8,fL,fR,dst));
1254 addInstr(env, AMD64Instr_Alu64R(Aalu_AND, AMD64RMI_Imm(0x45), dst));
1264 addInstr(env, AMD64Instr_SseSF2SI( 8, szD, rf, dst ));
1283 addInstr(env, mk_iMOVsd_RR(src,dst) );
1284 addInstr(env, AMD64Instr_Alu64R(Aalu_AND,
1298 addInstr(env, AMD64Instr_LoadEX(1,False,amode,dst));
1311 addInstr(env, AMD64Instr_LoadEX(2,False,amode,dst));
1338 addInstr(env, mk_iMOVsd_RR(reg,dst));
1339 addInstr(env, AMD64Instr_Alu32R(aluOp, rmi, dst));
1351 addInstr(env, AMD64Instr_MovxLQ(e->Iex.Unop.op == Iop_32Sto64,
1375 addInstr(env, mk_iMOVsd_RR(src,dst) );
1376 addInstr(env, AMD64Instr_Alu64R(Aalu_AND,
1390 addInstr(env, mk_iMOVsd_RR(src,dst) );
1391 addInstr(env, AMD64Instr_Sh64(Ash_SHL, amt, dst));
1392 addInstr(env, AMD64Instr_Sh64(Ash_SAR, amt, dst));
1401 addInstr(env, mk_iMOVsd_RR(src,dst) );
1402 addInstr(env, AMD64Instr_Unary64(Aun_NOT,dst));
1417 addInstr(env, mk_iMOVsd_RR(src,dst) );
1418 addInstr(env, AMD64Instr_Sh64(Ash_SHR, shift, dst));
1426 addInstr(env, AMD64Instr_Set64(cond,dst));
1436 addInstr(env, AMD64Instr_Set64(cond,dst));
1437 addInstr(env, AMD64Instr_Sh64(Ash_SHL, 63, dst));
1438 addInstr(env, AMD64Instr_Sh64(Ash_SAR, 63, dst));
1445 addInstr(env, AMD64Instr_Bsfr64(True,src,dst));
1455 addInstr(env, AMD64Instr_Bsfr64(False,src,tmp));
1456 addInstr(env, AMD64Instr_Alu64R(Aalu_MOV,
1458 addInstr(env, AMD64Instr_Alu64R(Aalu_SUB,
1466 addInstr(env, mk_iMOVsd_RR(src,dst));
1467 addInstr(env, AMD64Instr_Unary64(Aun_NEG,dst));
1468 addInstr(env, AMD64Instr_Alu64R(Aalu_OR,
1470 addInstr(env, AMD64Instr_Sh64(Ash_SAR, 63, dst));
1478 addInstr(env, mk_iMOVsd_RR(pre,src));
1479 addInstr(env, AMD64Instr_MovxLQ(False, src, src));
1480 addInstr(env, mk_iMOVsd_RR(src,dst));
1481 addInstr(env, AMD64Instr_Unary64(Aun_NEG,dst));
1482 addInstr(env, AMD64Instr_Alu64R(Aalu_OR,
1484 addInstr(env, AMD64Instr_Sh64(Ash_SAR, 63, dst));
1494 addInstr(env, mk_iMOVsd_RR(src, dst));
1495 addInstr(env, AMD64Instr_Unary64(Aun_NEG, dst));
1496 addInstr(env, AMD64Instr_Alu64R(Aalu_OR, AMD64RMI_Reg(src), dst));
1504 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vec, rsp_m16));
1505 addInstr(env, AMD64Instr_LoadEX(4, False/*z-widen*/, rsp_m16, dst));
1518 addInstr(env, AMD64Instr_SseLdSt(False/*store*/,
1520 addInstr(env, AMD64Instr_Alu64R( Aalu_MOV,
1544 addInstr(env, AMD64Instr_SseLdSt(False/*store*/,
1546 addInstr(env, AMD64Instr_Alu64R( Aalu_MOV,
1560 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 8, src, m8_rsp));
1561 addInstr(env, AMD64Instr_Alu64R(
1575 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 4, src, m8_rsp));
1576 addInstr(env, AMD64Instr_LoadEX(4, False/*unsigned*/, m8_rsp, dst ));
1612 addInstr(env, mk_iMOVsd_RR(arg, hregAMD64_RDI()) );
1613 addInstr(env, AMD64Instr_Call( Acc_ALWAYS, (ULong)fn, 1 ));
1614 addInstr(env, mk_iMOVsd_RR(hregAMD64_RAX(), dst));
1625 addInstr(env, AMD64Instr_Alu64R(
1635 addInstr(env, AMD64Instr_LoadEX(
1652 addInstr(env, AMD64Instr_LoadEX( 1, False, am, dst ));
1656 addInstr(env, AMD64Instr_Alu64R( Aalu_MOV, AMD64RMI_Mem(am), dst ));
1678 addInstr(env, mk_iMOVsd_RR(hregAMD64_RAX(), dst));
1680 addInstr(env, AMD64Instr_MovxLQ(False, hregAMD64_RAX(), dst));
1690 addInstr(env, AMD64Instr_Imm64(e->Iex.Const.con->Ico.U64, r));
1695 addInstr(env, AMD64Instr_Alu64R(Aalu_MOV, rmi, r));
1707 addInstr(env, mk_iMOVsd_RR(rX,dst));
1709 addInstr(env, AMD64Instr_Test64(0xFF, r8));
1710 addInstr(env, AMD64Instr_CMov64(Acc_Z,r0,dst));
1727 addInstr(env, AMD64Instr_A87Free(2));
1730 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 8, arg2, m8_rsp));
1731 addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 8));
1734 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 8, arg1, m8_rsp));
1735 addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 8));
1739 addInstr(env, AMD64Instr_A87FpOp(Afp_PREM));
1742 addInstr(env, AMD64Instr_A87FpOp(Afp_PREM1));
1749 addInstr(env, AMD64Instr_A87StSW(m8_rsp));
1750 addInstr(env, AMD64Instr_Alu64R(Aalu_MOV,AMD64RMI_Mem(m8_rsp),dst));
1751 addInstr(env, AMD64Instr_Alu64R(Aalu_AND,AMD64RMI_Imm(0x4700),dst));
2059 addInstr(env, mk_iMOVsd_RR(r64,dst));
2060 addInstr(env, AMD64Instr_Alu64R(Aalu_AND,AMD64RMI_Imm(1),dst));
2071 addInstr(env, AMD64Instr_Alu64R(Aalu_MOV,AMD64RMI_Imm(0),r));
2072 addInstr(env, AMD64Instr_Alu64R(Aalu_XOR,AMD64RMI_Reg(r),r));
2087 addInstr(env, AMD64Instr_Test64(1,reg));
2096 addInstr(env, AMD64Instr_Test64(1,reg));
2106 addInstr(env, AMD64Instr_Test64(0xFF,r));
2116 addInstr(env, AMD64Instr_Test64(0xFFFF,r));
2127 addInstr(env, AMD64Instr_Alu32R(Aalu_CMP,rmi2,r1));
2142 addInstr(env, mk_iMOVsd_RR(r0, tmp));
2143 addInstr(env, AMD64Instr_Alu64R(Aalu_OR,rmi1,tmp));
2153 addInstr(env, AMD64Instr_Alu64R(Aalu_CMP,rmi2,r1));
2168 addInstr(env, mk_iMOVsd_RR(r1,r));
2169 addInstr(env, AMD64Instr_Alu64R(Aalu_XOR,rmi2,r));
2170 addInstr(env, AMD64Instr_Alu64R(Aalu_AND,AMD64RMI_Imm(0xFF),r));
2187 addInstr(env, mk_iMOVsd_RR(r1,r));
2188 addInstr(env, AMD64Instr_Alu64R(Aalu_XOR,rmi2,r));
2189 addInstr(env, AMD64Instr_Alu64R(Aalu_AND,AMD64RMI_Imm(0xFFFF),r));
2211 addInstr(env, AMD64Instr_Imm64(con->Iex.Const.con->Ico.U64, tmp));
2212 addInstr(env, AMD64Instr_Alu64R(Aalu_CMP,
2229 addInstr(env, AMD64Instr_Alu64R(Aalu_CMP,rmi2,r1));
2253 addInstr(env, AMD64Instr_Alu32R(Aalu_CMP,rmi2,r1));
2319 addInstr(env, mk_iMOVsd_RR(rRight, hregAMD64_RAX()));
2320 addInstr(env, AMD64Instr_MulL(syned, rmLeft));
2322 addInstr(env, mk_iMOVsd_RR(hregAMD64_RDX(), tHi));
2323 addInstr(env, mk_iMOVsd_RR(hregAMD64_RAX(), tLo));
2340 addInstr(env, mk_iMOVsd_RR(sHi, hregAMD64_RDX()));
2341 addInstr(env, mk_iMOVsd_RR(sLo, hregAMD64_RAX()));
2342 addInstr(env, AMD64Instr_Div(syned, 8, rmRight));
2343 addInstr(env, mk_iMOVsd_RR(hregAMD64_RDX(), tHi));
2344 addInstr(env, mk_iMOVsd_RR(hregAMD64_RAX(), tLo));
2399 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 4, res, am));
2411 addInstr(env, AMD64Instr_SseSDSS(True/*D->S*/,src,dst));
2420 addInstr(env, AMD64Instr_SseLdSt( True/*load*/, 4, res, am ));
2431 addInstr(env, AMD64Instr_Store(4, src, m4_rsp));
2432 addInstr(env, AMD64Instr_SseLdSt( True/*load*/, 4, dst, m4_rsp ));
2447 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 4, arg, m8_rsp));
2448 addInstr(env, AMD64Instr_A87Free(1));
2449 addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 4));
2450 addInstr(env, AMD64Instr_A87FpOp(Afp_ROUND));
2451 addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/, 4));
2452 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 4, dst, m8_rsp));
2532 addInstr(env, AMD64Instr_Imm64(u.u64, tmp));
2533 addInstr(env, AMD64Instr_Push(AMD64RMI_Reg(tmp)));
2534 addInstr(env, AMD64Instr_SseLdSt(
2547 addInstr(env, AMD64Instr_SseLdSt( True/*load*/, 8, res, am ));
2555 addInstr(env, AMD64Instr_SseLdSt( True/*load*/, 8, res, am ));
2565 addInstr(env, AMD64Instr_SseLdSt( True/*load*/, 8, res, am ));
2583 addInstr(env, mk_vMOVsd_RR(argL, dst));
2586 addInstr(env, AMD64Instr_Sse64FLo(op, argR, dst));
2602 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 8, arg, m8_rsp));
2603 addInstr(env, AMD64Instr_A87Free(1));
2604 addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 8));
2605 addInstr(env, AMD64Instr_A87FpOp(Afp_ROUND));
2606 addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/, 8));
2607 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 8, dst, m8_rsp));
2631 addInstr(env, AMD64Instr_A87Free(2));
2634 addInstr(env, AMD64Instr_SseLdSt(
2636 addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 8));
2639 addInstr(env, AMD64Instr_SseLdSt(
2641 addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 8));
2648 addInstr(env, AMD64Instr_A87FpOp(Afp_SCALE));
2651 addInstr(env, AMD64Instr_A87FpOp(Afp_ATAN));
2654 addInstr(env, AMD64Instr_A87FpOp(Afp_YL2X));
2657 addInstr(env, AMD64Instr_A87FpOp(Afp_YL2XP1));
2660 addInstr(env, AMD64Instr_A87FpOp(Afp_PREM));
2663 addInstr(env, AMD64Instr_A87FpOp(Afp_PREM1));
2670 addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/, 8));
2671 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 8, dst, m8_rsp));
2679 addInstr(env, AMD64Instr_SseSI2SF( 8, 8, src, dst ));
2688 addInstr(env, AMD64Instr_SseSI2SF( 4, 8, src, dst ));
2703 addInstr(env, mk_vMOVsd_RR(src,tmp));
2704 addInstr(env, AMD64Instr_Push(AMD64RMI_Imm(0)));
2705 addInstr(env, AMD64Instr_Imm64( 1ULL<<63, r1 ));
2706 addInstr(env, AMD64Instr_Push(AMD64RMI_Reg(r1)));
2707 addInstr(env, AMD64Instr_SseLdSt(True, 16, dst, rsp0));
2710 addInstr(env, AMD64Instr_SseReRg(Asse_XOR, tmp, dst));
2712 addInstr(env, AMD64Instr_SseReRg(Asse_ANDN, tmp, dst));
2733 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 8, arg, m8_rsp));
2734 addInstr(env, AMD64Instr_A87Free(nNeeded));
2735 addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 8));
2738 addInstr(env, AMD64Instr_A87FpOp(fpop));
2741 addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/, 8));
2743 addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/, 8));
2744 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 8, dst, m8_rsp));
2754 //.. addInstr(env, X86Instr_Push(X86RMI_Reg(ri)));
2756 //.. addInstr(env, X86Instr_FpLdStI(
2770 addInstr(env, AMD64Instr_Alu64M(Aalu_MOV, src, m8_rsp));
2771 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 8, dst, m8_rsp));
2780 addInstr(env, AMD64Instr_SseSDSS(False/*S->D*/, f32, f64));
2797 addInstr(env, mk_vMOVsd_RR(rX,dst));
2798 addInstr(env, AMD64Instr_Test64(0xFF, r8));
2799 addInstr(env, AMD64Instr_SseCMov(Acc_Z,r0,dst));
2840 addInstr(env, AMD64Instr_SseLdSt(
2853 addInstr(env, AMD64Instr_SseLdSt( True/*load*/, 16, dst, am ));
2876 addInstr(env, AMD64Instr_SseLdSt( True/*load*/, 16, dst, rsp0 ));
2911 addInstr(env, AMD64Instr_SseReRg(Asse_CMPEQ32, arg, tmp));
2913 addInstr(env, AMD64Instr_SseShuf(0xB1, tmp, dst));
2914 addInstr(env, AMD64Instr_SseReRg(Asse_OR, tmp, dst));
2927 addInstr(env, mk_vMOVsd_RR(arg, tmp));
2928 addInstr(env, AMD64Instr_SseReRg(op, zero, tmp));
2940 addInstr(env, AMD64Instr_Sse32Fx4(op, arg, dst));
2949 addInstr(env, AMD64Instr_Sse64Fx2(op, arg, dst));
2966 addInstr(env, mk_vMOVsd_RR(arg, dst));
2967 addInstr(env, AMD64Instr_Sse32FLo(op, arg, dst));
2982 addInstr(env, mk_vMOVsd_RR(arg, dst));
2983 addInstr(env, AMD64Instr_Sse64FLo(op, arg, dst));
2991 addInstr(env, AMD64Instr_Alu64M(Aalu_MOV, ri, rsp_m32));
2992 addInstr(env, AMD64Instr_SseLdzLO(4, dst, rsp_m32));
3000 addInstr(env, AMD64Instr_Push(rmi));
3001 addInstr(env, AMD64Instr_SseLdzLO(8, dst, rsp0));
3027 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, srcV, rsp_m16));
3028 addInstr(env, AMD64Instr_Alu64M(Aalu_MOV, AMD64RI_Reg(srcI), rsp_m16));
3029 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, dst, rsp_m16));
3039 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, srcV, rsp_m16));
3040 addInstr(env, AMD64Instr_Store(4, srcI, rsp_m16));
3041 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, dst, rsp_m16));
3051 addInstr(env, AMD64Instr_Alu64M(Aalu_MOV, qHi, m8_rsp));
3052 addInstr(env, AMD64Instr_Alu64M(Aalu_MOV, qLo, m16_rsp));
3055 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, dst, m16_rsp));
3074 addInstr(env, mk_vMOVsd_RR(argL, dst));
3075 addInstr(env, AMD64Instr_Sse32Fx4(op, argR, dst));
3094 addInstr(env, mk_vMOVsd_RR(argL, dst));
3095 addInstr(env, AMD64Instr_Sse64Fx2(op, argR, dst));
3113 addInstr(env, mk_vMOVsd_RR(argL, dst));
3114 addInstr(env, AMD64Instr_Sse32FLo(op, argR, dst));
3132 addInstr(env, mk_vMOVsd_RR(argL, dst));
3133 addInstr(env, AMD64Instr_Sse64FLo(op, argR, dst));
3201 addInstr(env, mk_vMOVsd_RR(arg2, dst));
3202 addInstr(env, AMD64Instr_SseReRg(op, arg1, dst));
3204 addInstr(env, mk_vMOVsd_RR(arg1, dst));
3205 addInstr(env, AMD64Instr_SseReRg(op, arg2, dst));
3224 addInstr(env, AMD64Instr_Push(AMD64RMI_Imm(0)));
3225 addInstr(env, AMD64Instr_Push(rmi));
3226 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, ereg, rsp0));
3227 addInstr(env, mk_vMOVsd_RR(greg, dst));
3228 addInstr(env, AMD64Instr_SseReRg(op, ereg, dst));
3277 addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(48, hregAMD64_RSP()),
3280 addInstr(env, AMD64Instr_Alu64R(Aalu_AND,
3288 addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(0, argp),
3290 addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(16, argp),
3292 addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(32, argp),
3298 addInstr(env, AMD64Instr_SseLdSt(False/*!isLoad*/, 16, argL,
3300 addInstr(env, AMD64Instr_SseLdSt(False/*!isLoad*/, 16, argR,
3303 addInstr(env, AMD64Instr_Call( Acc_ALWAYS, (ULong)fn, 3 ));
3306 addInstr(env, AMD64Instr_SseLdSt(True/*isLoad*/, 16, dst,
3328 addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(48, hregAMD64_RSP()),
3331 addInstr(env, AMD64Instr_Alu64R(Aalu_AND,
3338 addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(0, argp),
3340 addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(16, argp),
3345 addInstr(env, AMD64Instr_SseLdSt(False/*!isLoad*/, 16, argL,
3348 addInstr(env, mk_iMOVsd_RR(argR, hregAMD64_RDX()));
3351 addInstr(env, AMD64Instr_Call( Acc_ALWAYS, (ULong)fn, 3 ));
3354 addInstr(env, AMD64Instr_SseLdSt(True/*isLoad*/, 16, dst,
3371 addInstr(env, mk_vMOVsd_RR(rX,dst));
3372 addInstr(env, AMD64Instr_Test64(0xFF, r8));
3373 addInstr(env, AMD64Instr_SseCMov(Acc_Z,r0,dst));
3425 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vLo, am0));
3426 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vHi, am16));
3438 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vLo, am0));
3439 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vHi, am16));
3451 addInstr(env, mk_vMOVsd_RR(vHi, vLo));
3481 addInstr(env, AMD64Instr_Sse32Fx4(op, argHi, dstHi));
3482 addInstr(env, AMD64Instr_Sse32Fx4(op, argLo, dstLo));
3495 addInstr(env, AMD64Instr_Sse64Fx2(op, argHi, dstHi));
3496 addInstr(env, AMD64Instr_Sse64Fx2(op, argLo, dstLo));
3511 addInstr(env, mk_vMOVsd_RR(tmpHi, tmpLo));
3514 addInstr(env, AMD64Instr_SseReRg(Asse_CMPEQ32, argHi, tmpHi));
3515 addInstr(env, AMD64Instr_SseReRg(Asse_CMPEQ32, argLo, tmpLo));
3518 addInstr(env, AMD64Instr_SseShuf(0xB1, tmpHi, dstHi));
3519 addInstr(env, AMD64Instr_SseShuf(0xB1, tmpLo, dstLo));
3520 addInstr(env, AMD64Instr_SseReRg(Asse_OR, tmpHi, dstHi));
3521 addInstr(env, AMD64Instr_SseReRg(Asse_OR, tmpLo, dstLo));
3536 addInstr(env, mk_vMOVsd_RR(argHi, tmpHi));
3537 addInstr(env, mk_vMOVsd_RR(argLo, tmpLo));
3538 addInstr(env, AMD64Instr_SseReRg(op, zero, tmpHi));
3539 addInstr(env, AMD64Instr_SseReRg(op, zero, tmpLo));
3568 addInstr(env, mk_vMOVsd_RR(argLhi, dstHi));
3569 addInstr(env, mk_vMOVsd_RR(argLlo, dstLo));
3570 addInstr(env, AMD64Instr_Sse64Fx2(op, argRhi, dstHi));
3571 addInstr(env, AMD64Instr_Sse64Fx2(op, argRlo, dstLo));
3590 addInstr(env, mk_vMOVsd_RR(argLhi, dstHi));
3591 addInstr(env, mk_vMOVsd_RR(argLlo, dstLo));
3592 addInstr(env, AMD64Instr_Sse32Fx4(op, argRhi, dstHi));
3593 addInstr(env, AMD64Instr_Sse32Fx4(op, argRlo, dstLo));
3609 addInstr(env, mk_vMOVsd_RR(argLhi, dstHi));
3610 addInstr(env, mk_vMOVsd_RR(argLlo, dstLo));
3611 addInstr(env, AMD64Instr_SseReRg(op, argRhi, dstHi));
3612 addInstr(env, AMD64Instr_SseReRg(op, argRlo, dstLo));
3642 addInstr(env, AMD64Instr_Alu64M(Aalu_MOV, q3, m8_rsp));
3643 addInstr(env, AMD64Instr_Alu64M(Aalu_MOV, q2, m16_rsp));
3644 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vHi, m16_rsp));
3646 addInstr(env, AMD64Instr_Alu64M(Aalu_MOV, q1, m8_rsp));
3647 addInstr(env, AMD64Instr_Alu64M(Aalu_MOV, q0, m16_rsp));
3648 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vLo, m16_rsp));
3688 addInstr(env, AMD64Instr_Alu64M(Aalu_MOV,ri,am));
3694 addInstr(env, AMD64Instr_Store(
3702 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 8, r, am));
3708 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 4, r, am));
3714 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, r, am));
3723 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vLo, am0));
3724 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vHi, am16));
3737 addInstr(env,
3748 addInstr(env, AMD64Instr_Store(
3759 addInstr(env, AMD64Instr_SseLdSt( False/*store*/, 4, f32, am ));
3766 addInstr(env, AMD64Instr_SseLdSt( False/*store*/, 8, f64, am ));
3773 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vec, am));
3782 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vLo, am0));
3783 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vHi, am16));
3801 addInstr(env, AMD64Instr_SseLdSt( False/*store*/, 8, val, am ));
3806 addInstr(env, AMD64Instr_Store( 1, r, am ));
3811 addInstr(env, AMD64Instr_Alu64M( Aalu_MOV, ri, am ));
3838 addInstr(env, AMD64Instr_Alu64R(Aalu_MOV, AMD64RMI_Reg(src), dst));
3840 addInstr(env, AMD64Instr_Lea64(am,dst));
3849 addInstr(env, AMD64Instr_Alu64R(Aalu_MOV,rmi,dst));
3856 addInstr(env, mk_iMOVsd_RR(rHi,dstHi) );
3857 addInstr(env, mk_iMOVsd_RR(rLo,dstLo) );
3863 addInstr(env, AMD64Instr_Set64(cond, dst));
3869 addInstr(env, mk_vMOVsd_RR(src, dst));
3875 addInstr(env, mk_vMOVsd_RR(src, dst));
3881 addInstr(env, mk_vMOVsd_RR(src, dst));
3888 addInstr(env, mk_vMOVsd_RR(rHi,dstHi) );
3889 addInstr(env, mk_vMOVsd_RR(rLo,dstLo) );
3920 addInstr(env, mk_iMOVsd_RR(hregAMD64_RAX(),dst) );
3930 addInstr(env, AMD64Instr_MFence());
3951 addInstr(env, mk_iMOVsd_RR(rExpd, rOld));
3952 addInstr(env, mk_iMOVsd_RR(rExpd, hregAMD64_RAX()));
3953 addInstr(env, mk_iMOVsd_RR(rData, hregAMD64_RBX()));
3961 addInstr(env, AMD64Instr_ACAS(am, sz));
3962 addInstr(env, AMD64Instr_CMov64(
3994 addInstr(env, mk_iMOVsd_RR(rExpdHi, rOldHi));
3995 addInstr(env, mk_iMOVsd_RR(rExpdLo, rOldLo));
3996 addInstr(env, mk_iMOVsd_RR(rExpdHi, hregAMD64_RDX()));
3997 addInstr(env, mk_iMOVsd_RR(rExpdLo, hregAMD64_RAX()));
3998 addInstr(env, mk_iMOVsd_RR(rDataHi, hregAMD64_RCX()));
3999 addInstr(env, mk_iMOVsd_RR(rDataLo, hregAMD64_RBX()));
4000 addInstr(env, AMD64Instr_DACAS(am, sz));
4001 addInstr(env,
4004 addInstr(env,
4045 addInstr(env, AMD64Instr_XDirect(stmt->Ist.Exit.dst->Ico.U64,
4052 addInstr(env, AMD64Instr_XAssisted(r, amRIP, cc, Ijk_Boring));
4071 addInstr(env, AMD64Instr_XAssisted(r, amRIP, cc, stmt->Ist.Exit.jk));
4119 addInstr(env, AMD64Instr_XDirect(cdst->Ico.U64,
4128 addInstr(env, AMD64Instr_XAssisted(r, amRIP, Acc_ALWAYS,
4141 addInstr(env, AMD64Instr_XIndir(r, amRIP, Acc_ALWAYS));
4143 addInstr(env, AMD64Instr_XAssisted(r, amRIP, Acc_ALWAYS,
4166 addInstr(env, AMD64Instr_XAssisted(r, amRIP, Acc_ALWAYS, jk));
4268 addInstr(env, AMD64Instr_EvCheck(amCounter, amFailAddr));
4275 addInstr(env, AMD64Instr_ProfInc());
