Lines Matching full:loaded
52 * which loaded the line into cache.
86 line_loaded* loaded;
162 c->loaded[i].memline = 0;
163 c->loaded[i].use_base = 0;
164 c->loaded[i].dep_use = 0;
165 c->loaded[i].iaddr = 0;
601 c->loaded = CLG_MALLOC("cl.sim.cu_ic.2",
703 idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
720 i, idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
747 idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
762 i, idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
784 idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
799 i, idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
842 line_loaded* loaded = &(LL.loaded[idx]);
850 use->count, i, use->mask, loaded->memline, loaded->iaddr);
852 CLG_(current_state).collect, loaded->use_base);
854 if (CLG_(current_state).collect && loaded->use_base) {
855 (loaded->use_base)[off_LL_AcCost] += 1000 / use->count;
856 (loaded->use_base)[off_LL_SpLoss] += i;
863 loaded->memline = memline;
864 loaded->iaddr = CLG_(bb_base) + current_ii->instr_offset;
865 loaded->use_base = (CLG_(current_state).nonskipped) ?
887 idx, LL.loaded[idx].memline, LL.loaded[idx].iaddr,
902 i, idx, LL.loaded[idx].memline, LL.loaded[idx].iaddr,
930 line_loaded* loaded = &(cache->loaded[idx]); \
938 use->count, c, use->mask, loaded->memline, loaded->iaddr); \
940 CLG_(current_state).collect, loaded->use_base); \
942 if (CLG_(current_state).collect && loaded->use_base) { \
943 (loaded->use_base)[off_##L##_AcCost] += 1000 / use->count; \
944 (loaded->use_base)[off_##L##_SpLoss] += c; \
947 loaded->dep_use->mask |= use->mask; \
948 loaded->dep_use->count += use->count; \
954 loaded->memline = memline; \
955 loaded->iaddr = CLG_(bb_base) + current_ii->instr_offset; \
956 loaded->use_base = (CLG_(current_state).nonskipped) ? \
961 return cacheuse_LL_access(memline, loaded); \
986 if (I1.loaded[i].use_base)
991 if (D1.loaded[i].use_base)
996 if (LL.loaded[i].use_base)
