Lines Matching full:lwc1
821 itable.o ???? ? 8 \ ? \ __text __TEXT ? ? __cstring __TEXT * ? __data __DATA @ ?? ?] (~ Y ?? ? P U U Y 32 f dsp dsp2 mdmx mips16 mips16e mips32 mips32r2 mips3d mips64 mips64r2 mipsI mipsII mipsIII mipsIV mipsV r3900 sb1 smartmips vr4100 vr4120 vr5000 vr5400 vr5500 6.0x0,5.*,5.*,5.*,5.OP,6.0x5 SPECIAL RSVD mips.igen 6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0x20 mips32,mips32r2,mips64,mips64r2,mipsI,mipsII,mipsIII,mipsIV,mipsV,r3900,vr4100,vr5000 ADD 6.0x8,5.RS,5.RT,16.IMMEDIATE NORMAL ADDI 6.0x9,5.RS,5.RT,16.IMMEDIATE ADDIU 6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0x21 ADDU 6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0x24 AND 6.0xc,5.RS,5.RT,16.IMMEDIATE ANDI 6.0x4,5.RS,5.RT,16.OFFSET BEQ 6.0x14,5.RS,5.RT,16.OFFSET mips32,mips32r2,mips64,mips64r2,mipsII,mipsIII,mipsIV,mipsV,r3900,vr4100,vr5000 BEQL 6.0x1,5.RS,5.0x1,16.OFFSET REGIMM BGEZ 6.0x1,5.RS,5.0x11,16.OFFSET BGEZAL 6.0x1,5.RS,5.0x13,16.OFFSET BGEZALL 6.0x1,5.RS,5.0x3,16.OFFSET BGEZL 6.0x7,5.RS,5.0x0,16.OFFSET BGTZ 6.0x17,5.RS,5.0x0,16.OFFSET BGTZL 6.0x6,5.RS,5.0x0,16.OFFSET BLEZ 6.0x16,5.RS,5.0x0,16.OFFSET BLEZL 6.0x1,5.RS,5.0x0,16.OFFSET BLTZ 6.0x1,5.RS,5.0x10,16.OFFSET BLTZAL 6.0x1,5.RS,5.0x12,16.OFFSET BLTZALL 6.0x1,5.RS,5.0x2,16.OFFSET BLTZL 6.0x5,5.RS,5.RT,16.OFFSET BNE 6.0x15,5.RS,5.RT,16.OFFSET BNEL 6.0x0,20.CODE,6.0xd BREAK 6.0x0,5.RS,5.RT,10.0x0,6.0x1a DIV 6.0x0,5.RS,5.RT,10.0x0,6.0x1b DIVU 6.0x2,26.INSTR_INDEX J 6.0x3,26.INSTR_INDEX JAL 6.0x0,5.RS,5.0x0,5.RD,5.0x0,6.0x9 JALR 6.0x0,5.RS,10.0x0,5.0x0,6.0x8 JR 6.0x20,5.BASE,5.RT,16.OFFSET LB 6.0x24,5.BASE,5.RT,16.OFFSET LBU 6.0x21,5.BASE,5.RT,16.OFFSET LH 6.0x25,5.BASE,5.RT,16.OFFSET LHU 6.0x30,5.BASE,5.RT,16.OFFSET mips32,mips32r2,mips64,mips64r2,mipsII,mipsIII,mipsIV,mipsV,vr4100,vr5000 LL 6.0xf,5.0x0,5.RT,16.IMMEDIATE LUI 6.0x23,5.BASE,5.RT,16.OFFSET LW 4.0xc,2.ZZ,5.BASE,5.RT,16.OFFSET LWCz 6.0x22,5.BASE,5.RT,16.OFFSET LWL 6.0x26,5.BASE,5.RT,16.OFFSET LWR 6.0x0,10.0x0,5.RD,5.0x0,6.0x10 mips32,mips64,mipsI,mipsII,mipsIII,mipsIV,mipsV,r3900,vr4100,vr5000 MFHI 6.0x0,10.0x0,5.RD,5.0x0,6.0x12 MFLO 6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0xb mips32,mips32r2,mips64,mips64r2,mipsIV,mipsV,vr5000 MOVN 6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0xa MOVZ 6.0x0,5.RS,15.0x0,6.0x11 MTHI 6.0x0,5.RS,15.0x0,6.0x13 MTLO 6.0x0,5.RS,5.RT,10.0x0,6.0x18 mips32,mips64,mipsI,mipsII,mipsIII,mipsIV,mipsV,vr4100 MULT 6.0x0,5.RS,5.RT,10.0x0,6.0x19 MULTU 6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0x27 NOR 6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0x25 OR 6.0xd,5.RS,5.RT,16.IMMEDIATE ORI 6.0x33,5.BASE,5.HINT,16.OFFSET PREF 6.0x28,5.BASE,5.RT,16.OFFSET SB 6.0x38,5.BASE,5.RT,16.OFFSET SC 6.0x29,5.BASE,5.RT,16.OFFSET SH 6.0x0,5.0x0,5.RT,5.RD,5.SHIFT,6.0x0 mipsI,mipsII,mipsIII,mipsIV,mipsV,r3900,vr4100,vr5000 SLLa 6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0x4 SLLV 6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0x2a SLT 6.0xa,5.RS,5.RT,16.IMMEDIATE SLTI 6.0xb,5.RS,5.RT,16.IMMEDIATE SLTIU 6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0x2b SLTU 6.0x0,5.0x0,5.RT,5.RD,5.SHIFT,6.0x3 SRA 6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0x7 SRAV 6.0x0,5.0x0,5.RT,5.RD,5.SHIFT,6.0x2 SRL 6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0x6 SRLV 6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0x22 SUB 6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0x23 SUBU 6.0x2b,5.BASE,5.RT,16.OFFSET SW 4.0xe,2.ZZ,5.BASE,5.RT,16.OFFSET SWCz 6.0x2a,5.BASE,5.RT,16.OFFSET SWL 6.0x2e,5.BASE,5.RT,16.OFFSET SWR 6.0x0,15.0x0,5.STYPE,6.0xf SYNC 6.0x0,20.CODE,6.0xc SYSCALL 6.0x0,5.RS,5.RT,10.CODE,6.0x34 TEQ 6.0x1,5.RS,5.0xc,16.IMMEDIATE TEQI 6.0x0,5.RS,5.RT,10.CODE,6.0x30 TGE 6.0x1,5.RS,5.0x8,16.IMMEDIATE TGEI 6.0x1,5.RS,5.0x9,16.IMMEDIATE TGEIU 6.0x0,5.RS,5.RT,10.CODE,6.0x31 TGEU 6.0x0,5.RS,5.RT,10.CODE,6.0x32 TLT 6.0x1,5.RS,5.0xa,16.IMMEDIATE TLTI 6.0x1,5.RS,5.0xb,16.IMMEDIATE TLTIU 6.0x0,5.RS,5.RT,10.CODE,6.0x33 TLTU 6.0x0,5.RS,5.RT,10.CODE,6.0x36 TNE 6.0x1,5.RS,5.0xe,16.IMMEDIATE TNEI 6.0x0,5.RS,5.RT,5.RD,5.0x0,6.0x26 XOR 6.0xe,5.RS,5.RT,16.IMMEDIATE XORI 6.0x11,2.0x2,3.FMT,5.0x0,5.FS,5.FD,6.0x5 COP1 32,f ABS.fmt 6.0x11,2.0x2,3.FMT,5.FT,5.FS,5.FD,6.0x0 ADD.fmt 6.0x11,5.0x8,3.CC,1.ND,1.TF,16.OFFSET COP1S mips32,mips32r2,mips64,mips64r2,mipsIV,mipsV,r3900,vr5000 BC1b 6.0x11,2.0x2,3.FMT,5.FT,5.FS,3.CC,2.0x0,2.0x3,4.COND mips32,mips32r2,mips64,mips64r2,mipsIV,mipsV,r3900,vr4100,vr5000 C.cond.fmtb 6.0x11,2.0x2,3.FMT,5.0x0,5.FS,5.FD,6.0xa mips32r2,mips64,mips64r2,mipsIII,mipsIV,mipsV,r3900,vr4100,vr5000 CEIL.L.fmt 6.0x11,2.0x2,3.FMT,5.0x0,5.FS,5.FD,6.0xe CEIL.W 6.0x11,5.0x2,5.RT,5.FS,11.0x0 mipsIV,r3900,vr4100,vr5000 CFC1b 6.0x11,5.0x6,5.RT,5.FS,11.0x0 CTC1b 6.0x11,2.0x2,3.FMT,5.0x0,5.FS,5.FD,6.0x21 CVT.D.fmt 6.0x11,2.0x2,3.FMT,5.0x0,5.FS,5.FD,6.0x25 CVT.L.fmt 6.0x11,2.0x2,3.FMT,5.0x0,5.FS,5.FD,6.0x20 CVT.S.fmt 6.0x11,2.0x2,3.FMT,5.0x0,5.FS,5.FD,6.0x24 CVT.W.fmt 6.0x11,2.0x2,3.FMT,5.FT,5.FS,5.FD,6.0x3 DIV.fmt 6.0x11,2.0x2,3.FMT,5.0x0,5.FS,5.FD,6.0xb FLOOR.L.fmt 6.0x11,2.0x2,3.FMT,5.0x0,5.FS,5.FD,6.0xf FLOOR.W.fmt 6.0x35,5.BASE,5.FT,16.OFFSET mips64,mips64r2,mipsIII,mipsIV,mipsV,r3900,vr4100,vr5000 LDC1b 6.0x31,5.BASE,5.FT,16.OFFSET LWC1
2659 load instruction lbu r%ld, %ld(r%ld) lw r%ld, %ld(r%ld) lh r%ld, %ld(r%ld) lb r%ld, %ld(r%ld) ldc1 f%ld, %ld(r%ld) lwc1 f%ld, %ld(r%ld) lwc%ld r%ld, %ld(r%ld) STORE AccessLength of %d would extend over %d bit aligned boundary for physical address 0x%s
