Lines Matching refs:MIPS
19 /* MIPS assembler and ARM->MIPS assembly translator
24 ** instruction is translated to one or more Mips instructions as necessary. This
27 ** significant performance gains on Mips compared to the generic pixel pipeline.
32 ** - The register allocator has been modified to re-map Arm registers 0-15 to mips
33 ** registers 2-17. Mips register 0 cannot be used as general-purpose register,
68 // Choose MIPS arch variant following gcc flags
209 // do not need this for MIPS, but it is in the Interface (virtual)
213 // for MIPS, any 32-bit immediate is OK
223 // for MIPS, any 32-bit immediate is OK
369 // used by the majority of data-processing ops. Many MIPS instructions
376 // note: tmpReg parameter defaults to 1, MIPS register AT
561 // conditional instruction. Under MIPS, this requires doing the comparison
780 Rn = R_sp; // convert LDR via Arm SP to LW via Mips SP
789 Rn = R_sp; // convert STR thru Arm SP to STR thru Mips SP
843 Rn = R_sp; // convert STR thru Arm SP to SW thru Mips SP
1225 #pragma mark MIPS Assembler...
1234 /* mips assembler
1342 // mArmPC[iArm] holds the value of the Mips-PC for the first MIPS
1652 // uses at2 register (mapped to some appropriate mips reg)
1662 // immediate version - uses at2 register (mapped to some appropriate mips reg)
