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    Searched defs:DefIdx (Results 1 - 9 of 9) sorted by null

  /external/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGSDNodes.h 136 unsigned DefIdx;
154 return DefIdx-1;
  /external/llvm/lib/CodeGen/
LiveRangeCalc.cpp 91 unsigned DefIdx;
95 } else if (MI->isRegTiedToDefOperand(I.getOperandNo(), &DefIdx)) {
98 if (MI->getOperand(DefIdx).isEarlyClobber())
TargetSchedule.cpp 129 unsigned DefIdx = 0;
133 ++DefIdx;
135 return DefIdx;
189 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
190 if (DefIdx < SCDesc->NumWriteLatencyEntries) {
193 STI->getWriteLatencyEntry(SCDesc, DefIdx);
209 // If DefIdx does not exist in the model (e.g. implicit defs), then return
216 ss << "DefIdx " << DefIdx << " exceeds machine model writes for "
237 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries
    [all...]
RegAllocFast.cpp 732 unsigned DefIdx = 0;
733 if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue;
735 << DefIdx << ".\n");
    [all...]
InlineSpiller.cpp 892 SlotIndex DefIdx = Edit->rematerializeAt(*MI->getParent(), MI, NewLI.reg, RM
    [all...]
MachineInstr.cpp 700 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
701 if (DefIdx != -1)
702 tieOperands(DefIdx, OpNo);
    [all...]
MachineVerifier.cpp 881 unsigned DefIdx;
883 MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
884 Reg != MI->getOperand(DefIdx).getReg())
    [all...]
RegisterCoalescer.cpp 600 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
601 assert(DefIdx != -1);
603 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
703 SlotIndex DefIdx = UseIdx.getRegSlot();
704 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
707 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
708 assert(DVNI->def == DefIdx);
    [all...]
  /external/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp     [all...]

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