| /external/llvm/lib/Target/Hexagon/ |
| HexagonSplitConst32AndConst64.cpp | 85 int DestReg = MI->getOperand(0).getReg();
89 TII->get(Hexagon::LO), DestReg).addOperand(Symbol);
91 TII->get(Hexagon::HI), DestReg).addOperand(Symbol);
98 int DestReg = MI->getOperand(0).getReg();
102 TII->get(Hexagon::LO_jt), DestReg).addOperand(Symbol);
104 TII->get(Hexagon::HI_jt), DestReg).addOperand(Symbol);
111 int DestReg = MI->getOperand(0).getReg();
115 TII->get(Hexagon::LO_label), DestReg).addOperand(Symbol);
117 TII->get(Hexagon::HI_label), DestReg).addOperand(Symbol);
124 int DestReg = MI->getOperand(0).getReg()
[all...] |
| HexagonSplitTFRCondSets.cpp | 97 int DestReg = MI->getOperand(0).getReg();
113 if (DestReg != SrcReg1) {
115 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1);
117 if (DestReg != SrcReg2) {
119 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2);
127 int DestReg = MI->getOperand(0).getReg();
132 if (DestReg != SrcReg1) {
134 TII->get(Hexagon::TFR_cPt), DestReg).
139 TII->get(Hexagon::TFRI_cNotPt), DestReg).
144 TII->get(Hexagon::TFRI_cNotPt_f), DestReg)
[all...] |
| HexagonCopyToCombine.cpp | 94 void emitCombineRR(MachineBasicBlock::iterator &Before, unsigned DestReg,
97 void emitCombineRI(MachineBasicBlock::iterator &Before, unsigned DestReg,
100 void emitCombineIR(MachineBasicBlock::iterator &Before, unsigned DestReg,
103 void emitCombineII(MachineBasicBlock::iterator &Before, unsigned DestReg,
122 unsigned DestReg = MI->getOperand(0).getReg();
124 return Hexagon::IntRegsRegClass.contains(DestReg) &&
132 unsigned DestReg = MI->getOperand(0).getReg();
135 return Hexagon::IntRegsRegClass.contains(DestReg) &&
150 unsigned DestReg = MI->getOperand(0).getReg();
151 return Hexagon::IntRegsRegClass.contains(DestReg);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 116 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
117 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
118 VRBase = DestReg;
120 } else if (DestReg != SrcReg)
159 // Figure out the register class to create for the destreg.
463 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
464 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
465 VRBase = DestReg;
503 // Create the destreg if it is missing.
518 // Figure out the register class to create for the destreg. It should b
[all...] |
| FunctionLoweringInfo.cpp | 286 unsigned DestReg = ValueMap[PN];
287 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
289 LiveOutRegInfo.grow(DestReg);
290 LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
|
| SelectionDAGISel.cpp | 559 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
560 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
571 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelDAGToDAG.cpp | 406 unsigned RdhwrOpc, SrcReg, DestReg;
411 DestReg = Mips::V1;
415 DestReg = Mips::V1_64;
422 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
424 SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 126 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
137 DestReg)
145 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
151 return DestReg;
|
| PPCRegisterInfo.cpp | 415 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
427 unsigned DestReg = MI.getOperand(0).getReg();
428 assert(MI.definesRegister(DestReg) &&
436 if (DestReg != PPC::CR0) {
440 unsigned ShiftBits = getEncodingValue(DestReg)*4;
447 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
482 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset>
491 unsigned DestReg = MI.getOperand(0).getReg();
492 assert(MI.definesRegister(DestReg) &&
498 BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg)
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600MachineScheduler.cpp | 304 unsigned DestReg = MI->getOperand(0).getReg();
305 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_XRegClass) ||
306 regBelongsToClass(DestReg, &AMDGPU::R600_AddrRegClass))
308 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_YRegClass))
310 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_ZRegClass))
312 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_WRegClass))
314 if (regBelongsToClass(DestReg, &AMDGPU::R600_Reg128RegClass))
385 unsigned DestReg = MI->getOperand(DstIndex).getReg();
392 MO.getReg() == DestReg)
395 // Constrains the regclass of DestReg to assign it to Slo
[all...] |
| /external/llvm/lib/CodeGen/ |
| PHIElimination.cpp | 231 unsigned DestReg = MPhi->getOperand(0).getReg();
248 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
260 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
264 TII->get(TargetOpcode::COPY), DestReg)
302 LV->addVirtualRegisterDead(DestReg, PHICopy);
303 LV->removeVirtualRegisterDead(DestReg, MPhi);
326 LiveInterval &DestLI = LIS->getInterval(DestReg);
341 // instruction from DestReg's live interval.
|
| StrongPHIElimination.cpp | 243 unsigned DestReg = BBI->getOperand(0).getReg();
244 addReg(DestReg);
251 unionRegs(DestReg, SrcReg);
287 unsigned DestReg = BBI->getOperand(0).getReg();
288 addReg(DestReg);
293 unionRegs(DestReg, SrcReg);
317 unsigned DestReg = PHI->getOperand(0).getReg();
318 if (!InsertedDestCopies.count(DestReg))
319 MergeLIsAndRename(DestReg, NewReg);
340 unsigned DestReg = I->first
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 625 unsigned DestReg = MI->getOperand(0).getReg();
678 BuildMI(*EndBB, StartOfEnd, DL, TII->get(AArch64::LSFP128_LDR), DestReg)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 531 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
533 DestReg)
535 return DestReg;
548 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
553 DestReg)
556 return DestReg;
597 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
609 TII.get(ARM::t2LDRpci), DestReg)
614 TII.get(ARM::LDRcp), DestReg)
618 return DestReg;
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
